ADNS-2220 Avago Technologies US Inc., ADNS-2220 Datasheet - Page 32

• Manufacturer Part Number: ADNS-2220
• Description: SOLID STATE OPTICAL MOUSE LENS
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2220

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q2072083A

Frame_Capture
Access: Read/Write
Data Type: Bit field
USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored
to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values
(see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any
firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware
must be reloaded using the SROM Download burst method.
This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst
register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically
incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536
times in a row. Both methods share the same pointer such that reading pixel values from this register will increment
the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at
the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the
Frame Capture description in the Synchronous Serial Port section for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
SROM_Enable
Access: Write
Data Type: 8-bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test.
Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The download will not be
successful unless this register contains the correct value.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from the Data_Out_Lower
and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test.
Reserved
32
Field
Field
Bit
Bit
FC
SE
7
7
7
7
FC
SE
6
6
6
6
SE
FC
5
5
Address: 0x13
Reset Value: 0x00
Address: 0x14
Reset Value: 0x00
5
Address: 0x15 – 0x18
5
SE
FC
4
4
4
4
SE
3
FC
3
3
3
SE
FC
2
2
2
2
SE
FC
1
1
1
1
SE
FC
0
0
0
0