FDD3672 Fairchild Semiconductor, FDD3672 Datasheet - Page 6

• Manufacturer Part Number: FDD3672
• Description: MOSFET N-CH 100V 44A D-PAK
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r
• Type: Power MOSFETr

Specifications of FDD3672

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 28 mOhm @ 44A, 10V
• Drain To Source Voltage (vdss): 100V
• Current - Continuous Drain (id) @ 25° C: 44A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 36nC @ 10V
• Input Capacitance (ciss) @ Vds: 1710pF @ 25V
• Power - Max: 135W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Number Of Elements: 1
• Polarity: N
• Channel Mode: Enhancement
• Drain-source On-res: 0.028Ohm
• Drain-source On-volt: 100V
• Gate-source Voltage (max): ±20V
• Drain Current (max): 6.5A
• Power Dissipation: 135W
• Output Power (max): Not RequiredW
• Frequency (max): Not RequiredMHz
• Noise Figure: Not RequireddB
• Power Gain: Not RequireddB
• Drain Efficiency: Not Required%
• Operating Temp Range: -55C to 175C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 2 +Tab
• Package Type: TO-252
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.028 Ohm @ 10 V
• Drain-source Breakdown Voltage: 100 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 6.5 A
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDD3672; FDD3672TR

©2010 Fairchild Semiconductor Corporation
Test Circuits and Waveforms
VARY t
REQUIRED PEAK I
V
0V
GS
I
Figure 14. Unclamped Energy Test Circuit
g(REF)
Figure 18. Switching Time Test Circuit
P
Figure 16. Gate Charge Test Circuit
TO OBTAIN
V
t
GS
P
V
GS
AS
R
GS
R
V
G
GS
V
DS
V
DUT
DS
V
I
AS
DS
L
DUT
R
DUT
L
0.01Ω
L
-
+
V
-
-
+
+
DD
V
V
DD
DD
0
Q
0
0
V
V
g(TH)
DS
GS
I
10%
V
Figure 15. Unclamped Energy Waveforms
g(REF)
0
0
DD
V
GS
Figure 19. Switching Time Waveforms
V
Figure 17. Gate Charge Waveforms
= 2V
GS
t
d(ON)
90%
50%
Q
t
ON
Q
gs
10%
gs2
t
r
I
AS
PULSE WIDTH
t
P
Q
gd
V
DS
Q
BV
g(TOT)
t
AV
DSS
t
d(OFF)
90%
V
t
DS
OFF
50%
V
t
GS
f
10%
FDD3672 Rev. A2
= 10V
V
DD
90%