LAN91C96I-MU SMSC, LAN91C96I-MU Datasheet - Page 23

• Manufacturer Part Number: LAN91C96I-MU
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96I-MU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Chapter 5 Functional Description
SMSC LAN91C96 5v&3v
Except for the bus interface, the functional behavior of the LAN91C96 after initial configuration is identical
for LOCAL BUS and PCMCIA modes.
The LAN91C96 includes an arbitrated shared memory of 6144 bytes. Any portion of this memory can be
used for receive or transmit packets.
The MMU unit allocates RAM memory to be used for transmit and receive packets, using 256 byte pages.
The arbitration is transparent to the CPU in every sense. There is no speed penalty for LOCAL BUS type
of machines due to arbitration. There are no restrictions on what locations can be accessed at any time.
RAM accesses as well as MMU requests are arbitrated.
The RAM is accessed by mapping it into I/O space for sequential access. Except for the RAM accesses
and the MMU request/release commands, I/O accesses are not arbitrated.
The I/O space is 16 bits wide. Provisions for 8 bit systems are handled by the bus interface.
In the system memory space, up to 64 kbytes are decoded by the LAN91C96 as expansion ROM. The
ROM expansion area is 8 bits wide.
Device configuration is done using a serial EEPROM, with support for modifications to the EEPROM at
installation time. A Flash ROM is supported for PCMCIA attribute memory.
The CSMA/CD core implements the 802.3 MAC layer protocol. It has two independent interfaces, the data
path and the control path.
Both interfaces are 16 bits wide. The control path provides a set of registers used to configure and control
the block. These registers are accessible by the CPU through the LAN91C96 I/O space. The data path is
of sequential access nature and typically works in one direction at any given time. An internal DMA type of
interface connects the data path to the device RAM through the arbiter and MMU.
The CSMA/CD data path interface is not accessible to the host CPU.
The internal DMA interface can arbitrate for RAM access and request memory from the MMU when
necessary.
An encoder/decoder block interfaces the CSMA/CD block on the serial side. The encoder will do the
Manchester encoding of the transmit data at 10 Mb/s, while the decoder will recover the receive clock, and
decode received data.
Carrier and Collision detection signals are also handled by this block and relayed to the CSMA/CD block.
The encoder/decoder block can interface the network through the AUI interface pairs, or it can be
programmed to use the internal 10BASE-T transceiver and connect to a twisted pair network.
The twisted pair interface takes care of the medium dependent signaling for 10BASE-T type of networks.
It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision
detection as well as the link integrity test function. The LAN91C96 provides a 16-bit data path into RAM.
The RAM is private and can only be accessed by the system via the arbiter. RAM memory is managed by
the MMU. Byte and word accesses to the RAM are supported.
If the system to SRAM bandwidth is insufficient the LAN91C96 will automatically use its IOCHRDY line for
flow control. However, for LOCAL BUS, IOCHRDY will never be negated.
DATASHEET
Page 23
Revision 1.0 (10-24-08)