LAN91C96I-MU SMSC, LAN91C96I-MU Datasheet - Page 55

• Manufacturer Part Number: LAN91C96I-MU
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96I-MU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Notes:
SMSC LAN91C96 5v&3v
Only command 2 uses N2, N1 and N0.
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
MMU commands releasing memory (commands 8 and A) should only be issued if the corresponding packet
number has memory allocated to it.
RESERVED
Can be used following 6 (to release receive packet memory in a more flexible way than 8).
1100
1110
The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET
MMU command, the RESET TX FIFOs does not release any memory.
COMMAND SEQUENCING
A second allocate command (command 2) should not be issued until the present one has completed.
Completion is determined by reading the FAILED bit of the allocation result register or through the
allocation interrupt. A second release command (commands 8 and A) should not be issued if the previous
one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing
command A, the contents of the PNR should not be changed until BUSY goes low. After issuing command
8, command 6 should not be issued until BUSY goes low. BUSY BIT - Readable at bit “0” of the MMU
command register address. When set indicates that MMU is still processing a release command. When
clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the
trailing edge of command.
I/O SPACE - BANK2
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is
accessible through the TX area. Some MMU commands use the number stored in this register as the
packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
RESERVED – This bit is reserved.
OFFSET
0
2
C)
F)
0
PACKET NUMBER REGISTER
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of
transmitting a packet just loaded into RAM. The packet number to be enqueued
is taken from the PACKET NUMBER REGISTER.
RESET TX FIFOs - This command will reset both TX FIFOs. The TX FIFO
holding the packet numbers awaiting transmission and the TX Completion FIFO.
This command provides a mechanism for canceling packet transmissions, and
reordering or bypassing the transmit queue.
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DATASHEET
NAME
Page 55
0
PACKET NUMBER AT TX AREA
0
READ/WRITE
TYPE
0
0
SYMBOL
PNR
Revision 1.0 (10-24-08)
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