LAN91C96I-MU SMSC, LAN91C96I-MU Datasheet - Page 49

• Manufacturer Part Number: LAN91C96I-MU
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96I-MU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Note 7.1
SMSC LAN91C96 5v&3v
of EN16*
function
16BIT
I/O SPACE - BANK1
The Configuration Register holds bits that define the device configuration and are not expected to change
during run-time. This register is part of the EEPROM saved setup in LOCAL BUS mode only. In PCMCIA
mode, this register is initialized to the state as defined below as if not EEPROM is present in LOCAL BUS
mode (ie. ENEEP Pin is a don’t care in PCMCIA mode)
NO WAIT - When set, does not request additional wait states. An exception to this are accesses
to the Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three
20MHz clocks on any cycle to the LAN91C96.
FULL STEP - This bit is used to select the signaling mode for the AUI port. When set the AUI port
uses full step signaling. Defaults low to half step signaling. This bit is only meaningful when AUI
SELECT is high.
SET SQLCH - When set, the squelch level used for the 10BASE-T receive signal is 240mV.
When clear the receive squelch level is 400mV. Defaults low.
AUI SELECT - When set the AUI interface is used, when clear the 10BASE-T interface is used.
Defaults low.
16BIT - Used in conjunction with EN16* and IO is 8 to define the width of the system bus. If the
EN16* pin is low, this bit is forced high. Otherwise the bit defaults low and can be programmed by
the host CPU.
DIS LINK - This bit is used to disable the 10BASE-T link test functions. When this bit is high the
LAN91C96 disables link test functions by not generating nor monitoring the network for link
pulses. In this mode the LAN91C96 will transmit packets regardless of the link test, the EPHSR
LINK_OK bit will be set and the LINK LED will stay on. When low the link test functions are
enabled. If the link status indicates FAIL, the EPHSR LINK_OK bit will be low, while transmit
packets enqueued will be processed by the LAN91C96, transmit data will not be sent out to the
cable.
pin
OFFSET
0
0
Bits 11, 10 and 9 are read only bits used by the software driver to transparently run on different controllers of
the LAN9000 family.
0
LAN91C90
FUTURE
FUTURE
FUTURE
DIS LINK
DEVICE
FEAST
X
0
CONFIGURATION REGISTER
BIT 11
X
1
0
0
0
1
1
DATASHEET
NAME
Reserved
BIT 10
WAIT
NO
0
1
1
0
1
0
0
Page 49
BIT 9
0
1
1
0
1
X
0
16
M
2
1
4
8
INT SEL1
STEP
FULL
READ/WRITE
0
0
MAX MEMORY SIZE
TYPE
256
256
(Note 7.1)
(Note 7.1)
(Note 7.1)
(Note 7.1)
256k
512k
INT SEL0
1M
SQLCH
SET
2=128k
1=64k
0
0
256
256
SYMBOL
Revision 1.0 (10-24-08)
CR
SELECT
AUI
0
X