COM20019I3V-DZD SMSC, COM20019I3V-DZD Datasheet - Page 30

• Manufacturer Part Number: COM20019I3V-DZD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20019I3V-DZD

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 312.5 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 11-07-08
2
1
0
7
6
5
4
3
BIT
BIT
Reconfiguration
Transmitter
Message
Acknowledged
Transmitter
Available
My
Reconfiguration
Duplicate ID
Receive
Activity
Token Seen
Excessive NAK
BIT NAME
BIT NAME
SYMBOL
RECON
TMA
TA
SYMBOL
MY-
RECON
DUPID
RCVACT
TOKEN
EXCNAK
Table 6.4 - Diagnostic Status Register
This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 656 S. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive reconfigurations caused by this
node.
This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit from Page fnn" command has been
acknowledged. This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never
acknowledged. The TMA bit is cleared by issuing the "Enable
Transmit from Page fnn" command.
This bit, if high, indicates that the transmitter is available for
transmitting. This bit is set when the last byte of scheduled
packet has been transmitted out, or upon execution of a "Disable
Transmitter" command. The TA bit is cleared by issuing the
"Enable Transmit from Page fnn" command after the node next
receives the token. This bit, when set, will cause an interrupt if
the corresponding bit in the IMR is also set.
This bit, if high, indicates that a past reconfiguration was caused
by this node. It is set when the Lost Token Timer times out, and
should be typically read following an interrupt caused by RECON.
Refer to the Improved Diagnostics section for further detail.
This bit, if high, indicates that the value in the Node ID Register
matches both Destination ID characters of the token and a
response to this token has occurred. Trailing zero's are also
verified. A logic "1" on this bit indicates a duplicate Node ID, thus
the user should write a new value into the Node ID Register. This
bit is only useful for duplicate ID detection when the device is off
line, that is, when the transmitter is disabled. When the device is
on line this bit will be set every time the device gets the token.
This bit is reset automatically upon reading the Diagnostic Status
Register. Refer to the Improved Diagnostics section for further
detail.
This bit, if high, indicates that data activity (logic "1") was
detected on the RXIN pin of the device. Refer to the Improved
Diagnostics section for further detail.
This bit, if high, indicates that a token has been seen on the
network, sent by a node other than this one. Refer to the
Improved Diagnostic section for further detail.
This bit, if high, indicates that either 128 or 4 Negative
Acknowledgements have occurred in response to the Free Buffer
Enquiry. This bit is cleared upon the "POR Clear Flags"
command. Reading the Diagnostic Status Register does not
clear this bit. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set. Refer to the Improved
Diagnostics section for further detail.
DATASHEET
Page 30
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
DESCRIPTION
DESCRIPTION
SMSC COM20019I 3.3V Rev.C