AD9912/PCBZ Analog Devices Inc, AD9912/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9912/PCBZ
• Description: Eval Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9912/PCBZ

• Kit Features: Flexible System Clock I/P Accepts Crystal
• Supported Devices: AD9912
• Tool / Board Applications: Direct Digital Synthesizer
• Development Tool Type: Hardware - Eval/Demo Board
• Mcu Supported Families: AD9912
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9912
• Primary Attributes: 14-Bit DAC, 48-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9912
Register 0x0011—Reserved
Register 0x0012—Reset (Autoclearing)
To reset the entire chip, the user can use the (non-autoclearing) soft reset bit in Register 0x0000.
Table 17.
Bits
0
Register 0x0013—Reset (Continued) (Not Autoclearing)
Table 18.
Bits
7
3
1
SYSTEM CLOCK (REGISTER 0x0020 TO REGISTER 0x0022)
Register 0x0020—N-Divider
Table 19.
Bits
[4:0]
Register 0x0021—Reserved
Register 0x0022—PLL Parameters
Table 20.
Bits
7
[6:4]
3
2
[1:0]
Bit Name
DDS reset
Bit Name
PD fund DDS
S-div/2 reset
S-divider reset
Bit Name
N-divider
Bit Name
VCO auto range
Reserved
2× reference
VCO range
Charge pump current
Description
Reset of the direct digital synthesis block. Reset of this block is very seldom needed.
Description
Setting this bit powers down the DDS fundamental output but not the spurs. It is used during tuning
of the SpurKiller circuit.
Asynchronous reset for S prescaler.
Synchronous (to S-divider prescaler output) reset for integer divider.
Description
These bits set the feedback divider for system clock PLL. There is a fixed divide-by-2 preceding this
block, as well as an offset of 2 added to this value. Therefore, setting this register to 00000 translates to
an overall feedback divider ratio of 4. See Figure 45.
Description
Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
Reserved.
Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by
the SYSCLK PLL. See Figure 44.
Selects low range or high range VCO.
0 = low range (700 MHz to 810 MHz).
1 = high range (900 MHz to 1000 MHz). For system clock settings between 810 MHz and 900 MHz, use
the VCO auto range (Bit 7) to set the correct VCO range automatically.
Charge pump current.
00 = 250 μA.
01 = 375 μA.
10 = off.
11= 125 μA.
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