MTB23P06VT4 ON Semiconductor, MTB23P06VT4 Datasheet - Page 7

• Manufacturer Part Number: MTB23P06VT4
• Description: MOSFET P-CH 60V 23A D2PAK
• Manufacturer: ON Semiconductor

Specifications of MTB23P06VT4

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 120 mOhm @ 11.5A, 10V
• Drain To Source Voltage (vdss): 60V
• Current - Continuous Drain (id) @ 25° C: 23A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 50nC @ 10V
• Input Capacitance (ciss) @ Vds: 1620pF @ 25V
• Power - Max: 90W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MTB23P06VT4OS

total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by T J(max) , the
maximum rated junction temperature of the die, R JA , the
thermal resistance from the device junction to ambient, and
the operating temperature, T A . Using the values provided
on the data sheet, P D can be calculated as follows:
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T A of 25 C,
one can calculate the power dissipation of the device. For a
D 2 PAK device, P D is calculated as follows.
Surface mount board layout is a critical portion of the
The power dissipation for a surface mount device is a
The values for the equation are found in the maximum
INFORMATION FOR USING THE D 2 PAK SURFACE MOUNT PACKAGE
P D =
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
T J(max) – T A
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
R JA
Figure 16. Thermal Resistance versus Drain Pad
Area for the D 2 PAK Package (Typical)
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MTB23P06V
7
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 3.0 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the drain pad. By increasing the area of the drain
pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
one will be giving up area on the printed circuit board
which can defeat the purpose of using surface mount
technology. For example, a graph of R JA versus drain pad
area is shown in Figure 16.
The 50 C/W for the D 2 PAK package assumes the use of
P D = 175 C – 25 C
inches
mm
50 C/W
= 3.0 Watts