AD676BD Analog Devices Inc, AD676BD Datasheet - Page 14

• Manufacturer Part Number: AD676BD
• Description: ADC Single SAR 100KSPS 16-Bit Parallel 28-Pin SBCDIP
• Manufacturer: Analog Devices Inc

Specifications of AD676BD

• Package: 28SBCDIP
• Resolution: 16 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 480mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-CDIP (0.600", 15.24mm)
• For Use With: AD676-EB - BOARD EVAL SAMPLING ADC AD676

AD676
MICROPROCESSOR INTERFACE
The AD676 is ideally suited for use in both traditional dc mea-
surement applications supporting a microprocessor, and in ac
signal processing applications interfacing to a digital signal pro-
cessor. The AD676 is designed to interface with a 16-bit data
bus, providing all output data bits in a single read cycle. A vari-
ety of external buffers, such as 74HC541, can be used with the
AD676 to provide 3-state outputs, high driving capability, and
to prevent bus noise from coupling into the ADC. The following
sections illustrate the use of the AD676 with a representative
digital signal processor and microprocessor. These circuits pro-
vide general interface practices which are applicable to other
processor choices.
ADSP-2101
Figure 10a shows the AD676 interfaced to the ADSP-2101 DSP
processor. The AD676 buffers are mapped in the ADSP-2101’s
memory space, requiring one wait state when using a 12.5 MHz
processor clock.
The falling edge of BUSY interrupts the processor, indicating
that new data is ready. The ADSP-2101 automatically jumps to
the appropriate service routine with minimal overhead. The in-
terrupt routine then instructs the processor to read the new data
using a memory read instruction.
Figure 10b shows circuitry which would be included by a typical
address decoder for the output buffers. In this case, a data
memory access to any address in the range 3000H to 37FFH
will result in the output buffers being enabled.
ADSP-2101
D8 – D23
IRQ2
DMS
A13
RD
A0
16
ADDRESS BUS
DECODER
CS
8
8
Figure 10a.
G1
74HC541
Y1 – Y8
G1
Y1 – Y8
74HC541
A1 – A3
A1 – A3
G2
G2
8
8
16
BUSY
BIT 1 – BIT 16
AD676
–14–
The AD676 CLK and SAMPLE can be generated by dividing
down the system clock as described earlier (Figure 3), or if the
ADSP-2101 serial port clocks are not being used, they can be
programmed to generate CLK and SAMPLE.
80286
The 80286 16-bit microprocessor can be interfaced to a buff-
ered AD676 without any generation of wait states. As seen in
Figure 11, BUSY can be used both to control the AD676 clock
and to alert the processor when new data is ready. In the system
shown, the 80286 should be configured in an edge triggered, di-
rect interrupt mode (integrated controller provides the interrupt
vector). Since the 80286 does not latch interrupt signals, the in-
terrupt needs to be internally acknowledged before BUSY goes
HIGH again during the next AD676 conversion (BUSY = 0).
Depending on whether the AD676 buffers are mapped into
memory or 1/0 space, the interrupt service routine will read the
data by using either the MOV or the IN instruction. To be able
to read all the 16 bits at once, and thereby increase the 80286’s
efficiency, the buffers should be located at an even address.
AD0 – AD15
80286
PCSO – 6
CLKOUT
INT 0
ALE
RD
S2
DECODER
DMS
A13
A12
A11
74HC04
CS
DIVIDER
16
Figure 10b.
Figure 11.
8
8
G1
Y1 – Y8
G1
Y1 – Y8
74HC541
74HC541
D
CLR
A1 – A8
A1 – A8
Q
Q
74HC74
G2
G2
D
CLR
8
8
Q
Q
2MHz
CS
16
BIT1 – BIT16
BUSY
SAMPLE
CLK
AD676
REV. A