AD676BD Analog Devices Inc, AD676BD Datasheet - Page 9

• Manufacturer Part Number: AD676BD
• Description: ADC Single SAR 100KSPS 16-Bit Parallel 28-Pin SBCDIP
• Manufacturer: Analog Devices Inc

Specifications of AD676BD

• Package: 28SBCDIP
• Resolution: 16 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 480mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-CDIP (0.600", 15.24mm)
• For Use With: AD676-EB - BOARD EVAL SAMPLING ADC AD676

CONTINUOUS CONVERSION
For maximum throughput rate, the AD676 can be operated in a
continuous convert mode (see Figure 2b). This is accomplished
by utilizing the fact that SAMPLE will no longer be ignored af-
ter BUSY goes LOW, so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. If SAMPLE is already HIGH when BUSY goes LOW
at the end of a conversion, then an acquisition is immediately
initiated and t
ous conversion may be latched up to t
LOW or t
ever, it is preferred that latching occur on or after the falling
edge of BUSY.
Care must he taken to adhere to the minimum/maximum timing
requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINES
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is pos-
sible to run CLK continuously, even during the sample period.
However, CLK edges during the sampling period, and especially
when SAMPLE goes LOW, may inject noise into the sampling
process. The AD676 is tested with no CLK cycles during the
sampling period. The BUSY signal can be used to prevent the
clock from running during acquisition, as illustrated in Figure 3.
In this circuit BUSY is used to reset the circuitry which divides
the system clock down to provide the AD676 CLK. This serves
to interrupt the clock until after the input signal has been ac-
quired, which has occurred when BUSY goes HIGH. When the
conversion is completed and BUSY goes LOW, the circuit in
Figure 3 truncates the 17th CLK pulse width which is tolerable
because only its rising edge is critical.
REV. A
12.288MHz
SYSTEM
CLOCK
OD
13
12
11
4
9
6
2
1
after the rising edge of the 17th clock pulse. How-
S
74HC175
74HC393
1D
1CLK
1QD
1CLR
3Q
CLK
2CLR
2CLK
and t
C
start from that time. Data from the previ-
CLR
2QC
2QD
2Q
1Q
3D
2D
Figure 3.
12
1
2
5
9
8
7
SD
before BUSY goes
10
7
BUSY
CLK
AD676
SAMPLE
9
–9–
Figure 3 also illustrates the use of a counter (74HC393) to de-
rive the AD676 SAMPLE command from the system clock
when a continuous convert mode is desirable. Pin 9 (2QC) pro-
vides a 96 kHz sample rate for the AD676 when used with a
12.288 MHz system clock. Alternately, Pin 8 (2QD) could be
used for a 48 kHz rate.
If a continuous clock is used, then the user must avoid CLK
edges at the instant of disconnecting V
falling edge of SAMPLE (see t
of CLK may vary, but both the HIGH (t
phases must conform to those shown in the timing specifica-
tions. The internal comparator makes its decisions on the rising
edge of CLK. To avoid a negative edge transition disturbing the
comparator’s settling, t
To also avoid transitions disturbing the internal comparator’s
settling, it is not recommended that the SAMPLE pin change
state toward the end of a CLK cycle.
During a conversion, internal dc error terms such as comparator
voltage offset are sampled, stored on internal capacitors and
used to correct for their corresponding errors when needed. Be-
cause these voltages are stored on capacitors, they are subject to
leakage decay and so require refreshing. For this reason there is
a maximum conversion time t
SAMPLE goes HIGH to the completion of the 17th CLK pulse,
no more than 1000 s should elapse for specified performance.
However, there is no restriction to the maximum time between
conversions.
Output coding for the AD676 is twos complement, as shown in
Table I. By inverting the MSB, the coding can be converted to
offset binary. The AD676 is designed to limit output coding in
the event of out-of-range inputs.
V
>Full Scale
Full Scale
Full Scale – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–Full Scale + 1 LSB
–Full Scale
<–Full Scale
IN
Table I. Output Coding
CL
should be at least half the value of t
C
SC
(1000 s). From the time
specification). The duty cycle
Output Code
011 . . . 11
011 . . . 11
011 . . . 10
000 . . . 01
000 . . . 00
111 . . . 11
100 . . . 01
100 . . . 00
100 . . . 00
IN
CH
which occurs at the
) and LOW (t
AD676
CL
CLK
)
.