85310AYI-11LF Integrated Device Technology (Idt), 85310AYI-11LF Datasheet - Page 10

• Manufacturer Part Number: 85310AYI-11LF
• Description: Clock Driver 2-IN ECL/LVPECL 32-Pin LQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 85310AYI-11LF

• Package: 32LQFP
• Configuration: 1 x 2:1
• Input Signal Type: HCSL|LVDS|LVHSTL|LVPECL|SSTL
• Maximum Output Frequency: 700 MHz
• Operating Supply Voltage: -2.5|-3.3|3.3 V

ICS85310I-11 Data Sheet
Recommendations for Unused Input Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS Control Pins
The control pins have an internal pullup and pulldown; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 4A. 3.3V LVPECL Output Termination
ICS85310AYI-11 REVISION F JUNE 9, 2010
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
10
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4B. 3.3V LVPECL Output Termination
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2010 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input