85310AYI-11LF Integrated Device Technology (Idt), 85310AYI-11LF Datasheet - Page 3
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85310AYI-11LF
Manufacturer Part Number
85310AYI-11LF
Description
Clock Driver 2-IN ECL/LVPECL 32-Pin LQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.85310AYI-11LF.pdf
(18 pages)
Specifications of 85310AYI-11LF
Package
32LQFP
Configuration
1 x 2:1
Input Signal Type
HCSL|LVDS|LVHSTL|LVPECL|SSTL
Maximum Output Frequency
700 MHz
Operating Supply Voltage
-2.5|-3.3|3.3 V
ICS85310I-11 Data Sheet
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 input as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Applications Information, Wiring the Differential Input to Accept Single-ended Levels.
ICS85310AYI-11 REVISION F JUNE 9, 2010
nCLK[0:1]
CLK[0:1]
CLK_EN
nQ[0:9]
Biased; NOTE 1
Biased; NOTE 1
CLK_EN
CLK0 or CLK1
Q[0:9]
0
1
0
1
0
1
Inputs
Inputs
Selected Source
CLK0, nCLK0
CLK1, nCLK1
nCLK0 or nCLK1
Biased; NOTE 1
Biased; NOTE 1
Disabled
1
1
0
0
Disabled; LOW
Enabled
Q[0:9]
HIGH
HIGH
HIGH
Q[0:9]
LOW
LOW
LOW
Outputs
Outputs
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
nQ[0:9]
3
HIGH
HIGH
HIGH
LOW
LOW
LOW
Disabled; HIGH
Enabled
nQ[0:9]
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Differential to Differential
Differential to Differential
Input to Output Mode
Enabled
©2010 Integrated Device Technology, Inc.
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Polarity