82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 162
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82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
WAN PLL 100-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of 82V3280EQG
Package
100TQFP
Operating Temperature
-40 to 85 °C
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
82V3280EQG
Manufacturer:
IDT
Quantity:
20 000
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Table 62: Input/Output Clock Timing
9.6
Electrical Specifications
Note:
1. Typical delay provided as reference only.
2. ‘Peak to Peak Delay Variation’ is the delay variation that is guaranteed not to be exceeded for IN11 in Master/Slave operation.
3. Tested when IN11 is selected.
IDT82V3280
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
INPUT / OUTPUT CLOCK TIMING
Symbol
t
t
t
t
t
t
1
2
3
4
5
6
19.44 MHz Output Clock
19.44 MHz Input Clock
8 kHz Input Clock
8 kHz Output Clock
51.84 MHz Input Clock
51.84 MHz Output Clock
6.48 MHz Input Clock
6.48 MHz Output Clock
38.88 MHz Output Clock
25.92 MHz Input Clock
38.88 MHz Input Clock
25.92 MHz Output Clock
3
Figure 38. Input / Output Clock Timing
Typical Delay
1.4
t
t
t
t
t
t
1
4
1
1
2
3
2
3
4
5
6
1
(ns)
162
Peak to Peak Delay Variation
1.6
1.6
1.6
1.6
1.6
1.6
December 9, 2008
2
(ns)
WAN PLL
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