82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 70

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Programming Information
IDT82V3280
Address: 0AH
Type: Read / Write
Default Value: XXXXX001
7 - 3
Bit
2
1
0
7
-
OUT7_PECL_LVDS
OUT6_PECL_LVDS
OSC_EDGE
Name
-
6
-
Reserved.
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT7.
0: LVDS. (default)
1: PECL.
This bit selects a port technology for OUT6.
0: LVDS.
1: PECL. (default)
5
-
4
-
70
3
-
Description
OSC_EDGE
2
OUT7_PECL_LVDS
1
OUT6_PECL_LVDS
December 9, 2008
0
WAN PLL