82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 58
82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
WAN PLL 100-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of 82V3280EQG
Package
100TQFP
Operating Temperature
-40 to 85 °C
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Part Number:
82V3280EQG
Manufacturer:
IDT
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dard except the following:
Table 41: JTAG Timing Characteristics
JTAG
IDT82V3280
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
The JTAG interface timing diagram is shown in
• The output boundary scan cells do not capture data from the
• The TRST pin is set low by default and JTAG is disabled in order
Symbol
core and the device does not support EXTEST instruction;
to be consistent with other manufacturers.
t
TCK
t
t
t
S
H
D
TCK
TMS
TDI
JTAG
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
TCK period
Parameter
TDO
t
S
Figure 26. JTAG Interface Timing Diagram
Figure
26.
t
H
58
t
TCK
Min
100
25
25
t
D
Typ
Max
50
December 9, 2008
Unit
ns
ns
ns
ns
WAN PLL
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