MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 104

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

Table 43: WRITE Using Concurrent Auto Precharge
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
WRITE with auto precharge
From Command
(Bank n)
±
the WRITE diagrams show the nominal case, and where the two extreme cases (
[MIN] and
(page 105) shows the nominal case and the extremes of
pletion of a burst, assuming no other commands have been initiated, the DQ will re-
main High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 57 (page 106) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 58 (page 106). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 43.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-
charge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 59
(page 107).
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE,
cycles required to meet
WRITE burst may be followed by a subsequent PRECHARGE command.
met, as shown in Figure 61 (page 109).
of the data mask condition.
t
DQSS.
WRITE or WRITE with auto precharge
READ or READ with auto precharge
t
DQSS is specified with a relatively wide range (25% of one clock cycle). All of
t
PRECHARGE or ACTIVATE
WTR should be met, as shown in Figure 60 (page 108). The number of clock
t
DQSS [MAX]) might not be intuitive, they have also been included. Figure 56
To Command
(Bank m)
t
WTR is either 2 or
104
t
WR starts at the end of the data burst, regardless
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
512Mb: x4, x8, x16 DDR2 SDRAM
WTR/
(with Concurrent Auto Precharge)
t
CK, whichever is greater. Data for any
(CL - 1) + (BL/2) +
Minimum Delay
t
DQSS for BL = 4. Upon com-
(BL/2)
1
2004 Micron Technology, Inc. All rights reserved.
t
WTR
t
WR must be
t
WRITE
DQSS
Units
t
t
t
CK
CK
CK