MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 26

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

Table 10: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
Parameter/Condition
Operating burst read current: All banks
open, continuous burst reads, I
= 4, CL = CL (I
t
HIGH, CS# is HIGH between valid commands;
address bus inputs are switching; Data bus
inputs are switching
Burst refresh current:
fresh command at every
CKE is HIGH, CS# is HIGH between valid com-
mands; Other control and address bus inputs
are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V;
CKE ≤ 0.2V; Other control and address bus in-
puts are floating; Data bus inputs are float-
ing
Operating bank interleave read current:
All bank interleaving reads, I
4, CL = CL (I
t
(I
HIGH between valid commands; address bus
inputs are stable during deselects; Data bus
inputs are switching; See I
(page 24) for details
RAS =
CK =
DD
),
t
t
RCD =
CK (I
t
RAS MAX (I
DD
DD
t
DD
),
RCD (I
), AL =
t
), AL = 0;
RC =
DD
DD
DD
t
t
),
RCD (I
RC (I
Notes:
); CKE is HIGH, CS# is
Specifications and Conditions (Die Revision F) (Continued)
t
RP =
t
t
t
CK =
RFC (I
CK =
DD7
DD
DD
),
OUT
t
RP (I
) - 1 x
Conditions
t
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
OUT
t
CK (I
DD
RRD =
CK (I
= 0mA; BL =
) interval;
UDQS#. I
tion devices when operated outside of the range 0°C ≤ T
DD
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
DD
DD
DD1
= 0mA; BL
DD
DD
t
DD
); CKE is
CK (I
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
t
); re-
= 1.8V ±0.1V, V
RRD
),
DD4R
DD
DD
);
, and I
values must be met with all combinations of EMR bits 10 and 11.
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
Symbol
IN
IN
I
I
DD
I
I
I
DD4R
DD6L
DD
DD7
DD5
DD6
DD7
≤ V
≥ V
values must be derated (I
conditions:
DDQ
IL(AC)max
IH(AC)min
require A12 in EMR1 to be enabled during testing.
REF
= 1.8V ±0.1V, V
Configuration
26
= V
x4, x8, x16
Electrical Specifications – I
x4, x8
x4, x8
x4, x8
DDQ
x16
x16
x16
/2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DDL
512Mb: x4, x8, x16 DDR2 SDRAM
= 1.8V ±0.1V, V
DD
-25E/
205
275
230
230
300
370
-25
7
3
limits increase) on IT-option or on AT-op-
-3E/-3
180
235
180
185
240
350
7
3
C
REF
≤ 85°C:
= V
2004 Micron Technology, Inc. All rights reserved.
-37E
145
195
170
175
225
340
DDQ
7
3
/2.
DD
Parameters
115
155
165
170
220
340
-5E
C
7
3
≤ +85°C.
Units
mA
mA
mA
mA