MT48LC4M32B2TG-6:G Micron Technology Inc, MT48LC4M32B2TG-6:G Datasheet - Page 51

• Manufacturer Part Number: MT48LC4M32B2TG-6:G
• Description: DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2TG-6:G

• Density: 128 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 34:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
COMMAND
A0-A9, A11
Precharge all
BA0, BA1
DQM 0-3
active banks
CLK
CKE
A10
DQ
Power-Down Mode
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
Notes:
T0
t CMH
t CKH
t AH
Two clock cycles
1. Violating refresh requirements during power-down may result in a loss of data.
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
51
Exit power-down mode
(
(
(
(
(
(
)
)
)
(
)
(
)
(
(
(
)
(
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
)
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(
(
)
)
)
t CKS
Tn + 1
NOP
All banks idle
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Timing Diagrams
Tn + 2
ACTIVE
ROW
ROW
BANK
DON’T CARE
UNDEFINED