ISP1504CBS NXP Semiconductors, ISP1504CBS Datasheet - Page 36
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ISP1504CBS
Manufacturer Part Number
ISP1504CBS
Description
RF Transceiver USB2.0 ULPI OTG TRANSCEIVER
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1504ABS118.pdf
(83 pages)
Specifications of ISP1504CBS
Operating Supply Voltage
1.65 V to 3.6 V
Mounting Style
SMD/SMT
Package / Case
HVQFN
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISP1504CBS,157
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1504CBS
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
ISP1504CBSFA
Manufacturer:
NXP
Quantity:
6 041
NXP Semiconductors
Table 18.
ISP1504A_ISP1504C_3
Product data sheet
Packet sequence High-speed
Transmit-Transmit
(host only)
Receive-Transmit
(host or
peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or
peripheral)
Fig 15. High-speed transmit-to-transmit packet timing
CLOCK
DATA
DP or
DIR
[7:0]
STP
NXT
DM
D
N 1
Link decision times
D
N
link delay
15 to 24
1 to 14
1
92
DATA
TX end delay (two to five clocks)
Full-speed
link delay
7 to 18
7 to 18
1
80
EOP
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 03 — 7 April 2008
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
Definition
Number of clock cycles a host link must wait before driving
the TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the first
packet. The timing given ensures inter-packet delays of 2 bit
times to 6.5 bit times.
Number of clock cycles the link must wait before driving the
TXCMD for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; deassertion of DIR or an RXCMD, indicating
RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures inter-packet
delays of 2 bit times to 6.5 bit times.
Minimum number of clock cycles between consecutive
receive packets. The link must be able to receive both
packets.
Host or peripheral transmits a packet and will time-out after
this number of clock cycles if a response is not received. Any
subsequent transmission can occur after this time.
ISP1504A; ISP1504C
IDLE
ULPI HS USB OTG transceiver
(one to two clocks)
© NXP B.V. 2008. All rights reserved.
TXCMD
TX start delay
004aaa712
SYNC
D0
35 of 82
D1