ISP1505ABS NXP Semiconductors, ISP1505ABS Datasheet - Page 24
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ISP1505ABS
Manufacturer Part Number
ISP1505ABS
Description
RF Transceiver USB2.0/ULPI1.1 XCVR
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1505ABS557.pdf
(76 pages)
Specifications of ISP1505ABS
Number Of Receivers
5
Number Of Transmitters
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
HVQFN-24
Maximum Data Rate
480 Mbps
Maximum Supply Current
0.001 mA, 48 mA
Minimum Operating Temperature
- 40 C
Protocol Supported
USB 2.0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISP1505ABS,557
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1505ABS
Manufacturer:
NXP
Quantity:
13
NXP Semiconductors
Table 9.
Table 10.
DP_PULLDOWN = 0.
[1]
ISP1505A_ISP1505C_3
Product data sheet
DATA
1 to 0
3 to 2
5 to 4
6
7
Mode
XCVRSELECT[1:0]
TERMSELECT
LINESTATE[1:0]
Fig 6.
!squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.
DATA [ 7:0 ]
Single and back-to-back RXCMDs from the ISP1505 to the link
CLOCK
Name
LINESTATE
V
RxEvent
reserved
ALT_INT
RXCMD byte format
LINESTATE[1:0] encoding for upstream facing ports: peripheral
BUS
NXT
STP
DIR
9.5.2.1 Linestate encoding
state
[1]
00
01
10
11
LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1505 detects
a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]
value. The value given on LINESTATE[1:0] depends on the setting of various registers.
Table 10
peripherals.
which applies to host controllers. Dual-role devices must choose the correct table,
depending on whether it is in peripheral or host mode.
Description and value
LINESTATE signals: For a definition of LINESTATE, see
DATA0 — LINESTATE[0]
DATA1 — LINESTATE[1]
Encoded V
Encoded USB event signals: For an explanation of RxEvent, see
-
By default, this signal is not used and is not needed in typical designs. Optionally, the link can
enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding
changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.
Full-speed
01, 11
1
SE0
FS-J
FS-K
SE1
turnaround
shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to
BUS
Table 11
voltage state: For an explanation of the V
Single RXCMD
RXCMD
High-speed
00
0
squelch
!squelch
invalid
invalid
shows the LINESTATE[1:0] encoding for downstream facing ports,
Rev. 03 — 26 August 2008
turnaround
Chirp
00
1
squelch
!squelch and HS_Differential_Receiver_Output
!squelch and !HS_Differential_Receiver_Output
invalid
ULPI HS USB host and peripheral transceiver
turnaround
ISP1505A; ISP1505C
Section
BUS
Back-to-back RXCMDs
RXCMD
state, see
9.5.2.1.
Section
RXCMD
Section
9.5.2.4.
© NXP B.V. 2008. All rights reserved.
turnaround
9.5.2.2.
004aaa695
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