ISP1505ABS NXP Semiconductors, ISP1505ABS Datasheet - Page 33

• Manufacturer Part Number: ISP1505ABS
• Description: RF Transceiver USB2.0/ULPI1.1 XCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1505ABS

• Number Of Receivers: 5
• Number Of Transmitters: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-24
• Maximum Data Rate: 480 Mbps
• Maximum Supply Current: 0.001 mA, 48 mA
• Minimum Operating Temperature: - 40 C
• Protocol Supported: USB 2.0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1505ABS,557

NXP Semiconductors
ISP1505A_ISP1505C_3
Product data sheet
Fig 12. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1505 operates just as in full-speed mode, and sends all data with the full-speed rise
time and fall time. Whenever the link transmits a USB packet in preamble mode, the
ISP1505 will automatically send a preamble header at full-speed bit rate before sending
the link packet at low-speed bit rate. The ISP1505 will ensure a minimum gap of four
full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the
low-speed packet SYNC. The ISP1505 will drive a J for at least one full-speed bit time
after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.
An example transmit packet is shown in
In preamble mode, the ISP1505 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 03 — 26 August 2008
link decision time (1 to 14 clocks)
IDLE
Figure
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
13.
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2008. All rights reserved.
SYNC
D0
004aaa713
32 of 75
D1