ISP1505ABS NXP Semiconductors, ISP1505ABS Datasheet - Page 8

• Manufacturer Part Number: ISP1505ABS
• Description: RF Transceiver USB2.0/ULPI1.1 XCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1505ABS

• Number Of Receivers: 5
• Number Of Transmitters: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-24
• Maximum Data Rate: 480 Mbps
• Maximum Supply Current: 0.001 mA, 48 mA
• Minimum Operating Temperature: - 40 C
• Protocol Supported: USB 2.0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1505ABS,557

NXP Semiconductors
7. Functional description
ISP1505A_ISP1505C_3
Product data sheet
7.1 ULPI interface controller
7.2 USB data serializer and deserializer
7.3 Hi-Speed USB (USB 2.0) ATX
The ISP1505 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link.
The ULPI interface controller provides the following functions:
For more information on the ULPI protocol, see
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the
USB link sends a transmit command and data on the ULPI bus. The serializer performs
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the
serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end
of the packet. When the serializer is busy and cannot accept any more data, the ULPI
interface controller deasserts NXT.
The USB data deserializer decodes data received from the USB bus. When data is
received, the deserializer strips the SYNC and EOP patterns, and then performs
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and
then asserting NXT whenever a byte is ready. The deserializer also detects various
receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and
byte-alignment errors.
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for
USB peripheral, host and OTG implementations. The following circuitry is included:
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ULPI-compliant interface and register set
Allows full control over the USB peripheral, host and SRP functionality
Parses the USB transmit and receive data
Prioritizes the USB receive data, USB transmit data, interrupts and register operations
Low-power mode
External V
V
6-pin serial mode and 3-pin serial mode
Generates RXCMDs; status updates
Maskable interrupts
Differential drivers to transmit data at high-speed, full-speed and low-speed
Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
Squelch circuit to detect high-speed bus activity
BUS
monitoring, charging and discharging
BUS
source control
Rev. 03 — 26 August 2008
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
Section
9.
© NXP B.V. 2008. All rights reserved.
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