STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 25

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III.10 - Interrupt Controller
III.10.1 - Description
Three external pins are used to manage the inter-
rupts generated by the Multi-HDLC . The interrupts
have three main sources:
– The operating interrupts generated by the HDLC
– The interrupt generated by an abnormal working
– The non-activity of the microprocessor (Watch-
III.10.2 - Operating Interrupts (INT0 Pin)
There are five main sources of operating interrupts
in the Multi-HDLC circuit:
– The HDLC receiver,
– The HDLC transmitter,
– The CI receiver,
– The Monitor receiver,
– The Monitor transmitter.
When an interrupt is generated by one of these
functions, the interrupt controller:
– Collects all the information about the reasons of
– Stores them in external memory.
– Informs the microprocessor by positioning the
Three interrupt queues are built in external mem-
ory to store the information about the interrupts:
– A single queue for the HDLC receivers and
– One for the CI receivers
– One for the monitor receiver
The microprocessor takes the interrupts into ac-
count by reading the Interrupt Register (IR) of the
interrupt controller.
This register informs the microprocessor of the in-
terrupt source. The microprocessor will have infor-
mation about the interrupt source by reading the
corresponding interrupt queue (see Paragraph “In-
terrupt Register IR(38)
On an overflow of the circular interrupt queues and
an overrun or underrun of the different FIFO, the
INT0Pin is activated and the origin of the interrupt
is stored in the Interrupt Register.
A 16 bits register is associated with the Tx Monitor
interrupt. It informs the microprocessor of which
transmitter has generated the interrupt (see Para-
graph
TMIR(30)
receivers/transmitters, the CI receivers and the
monitor transmitters/receivers. INT0 Pin is re-
served for this use.
of the clock distribution. INT1 Pin is reserved for
this use.
dog). WDO Pin is reserved for this use.
this interrupt
INT0 pin in the high level.
transmitter
“Transmit
H
” on Page 71).
Monitor
H
” on Page 74).
Interrupt
Register
III.10.3 - Time Base Interrupts (INT1 Pin)
The Time base interrupt is generated when an ab-
sence or an abnormal working of clock distribution
is detected. The INT1 Pin is activated.
III.10.4 - Emergency Interrupts (WDO Pin)
The WDO signal is activated by an overflow of the
watchdog register.
III.10.5 - Interrupt Queues
There are three different interrupt queues:
– Tx and Rx HDLC interrupt queue
– Rx C/I interrupt queue
– Rx Monitor interrupt queue.
Their length can be defined by software.
For debugging function, each interrupt word of the
CI interrupt queue and monitor interrupt queue
can be followed by a time stamped word. It is com-
posed of a counter which runs in the range of
250 s. The counter is the same as the watchdog
counter. Consequently, the watchdog function
isn’t available at the same time.
III.11 - Watchdog
This function is used to control the activity of the
application. It is composed of a counter which
counts down from an initial value loaded in the
Timer register by the microprocessor.
If the microprocessor doesn’t reset this counter
before it is totally decremented, the external Pin
WDO is activated; this signal can be used to reset
the microprocessor and all the application.
The initial time value of the counter is programma-
ble from 0 to 15s in increments of 0.25ms.
At the reset of the component, the counter is auto-
matically initialized by the value corresponding to
512ms which are indicated in the Timer register.
The microprocessor must put WDR (IDCR Regis-
ter) to”1” to reset this counter and to confirm that
the application started correctly.
In the reverse case, the WDO signal could be used
to reset the board a second time.
III.12 - Reset
There are two possibilities to reset the circuit:
– by software,
– by hardware.
Each programmable register receives its default
value. After that, the default value of each data
register is stored in the associated memory except
for Time slot Assigner memory.
STLC5466
25/130