STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 35

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEL(i); : DELAYED Multiplex(i) with (0
OMV (i) : Output Multiplex Validated 0/7
N.B. If DOUT4 and DOUT5 are GCI Multiplexes: then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VI.7 - Switching Matrix Configuration Register
IMTD
TS0
TS1
SGV
bit15
SW1
SW0
: Increased Minimum Throughput Delay
: Tristate 0
: Tristate 1
: Pseudo Random Sequence Generator Validated
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.
If TDM is at 2048 kb/s,1/2 bit-time is 244 ns
If TDM is at 4096 kb/s,1/2 bit-time is 122 ns
OMVi =1, condition to have DOUT(i) pin active (0
OMVi =0, DOUT(i) pin is High impedance continuously (0
When SI = 0 (bit of CMDR, variable delay mode):
IMTD = 1, the minimum delay through the matrix memory is three time slots whatever the se-
lected TDM output.
IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the select-
ed TDM output. In this case the input TDM’s cannot be delayed versus the Frame Synchroni-
zation (use of IMCR is limited) and the output TDM’s cannot be advanced versus the Frame
Synchronization (use of OMCR is limited).
TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate: “0” is at low impedance, “1” is at low
impedance and the third state is high impedance.
TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain: “0” is at low impedance, “1” is at high
impedance.
TS1 = 1, the DOUT4/5 pins are tristate: “0” is at low impedance, “1” is at low impedance and
the third state is high impedance.
TS1 = 0, the DOUT4/5 pins are open drain: “0” is at low impedance, “1” is at high impedance.
SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the
related time slot(s).
SGV = 0, PRS Generator is reset.”0” are transmitted during the related time slot.
DEL (i)
X
1
1
1
0
0
0
M1
M0
ST (i) 1
0
0
1
1
0
1
1
DR64 DR44 DR24 DR04 AISD
ST (i) 0
0
1
0
1
1
0
1
i
Each bit is transmitted on the rising edge of the double clock without
delay. Bit0 is defined by Frame synchronization Signal.
Each bit is transmitted with 1/2 bit-time delay.
Each bit is transmitted with 1 bit-time delay.
Each bit is transmitted with 2 bit-time delay
Each bit is transmitted with 1/2 bit-time advance.
Each bit is transmitted with 1 bit-time advance.
Each bit is transmitted with 2 bit-time advance
After reset (0000)
7).
bit8
STEP for each Output Multiplex 0/7 delayed or not
bit7
H
ME
i
7).
SGC
i
SAV
7).
SGV
TS1
SMCR (0C)
STLC5466
TS0
35/130
IMTD
bit0
H