STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 76

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
CFR
VII.5 - Receive Command / Indicate Interrupt
VII.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
This word is located in the Command/Indicate interrupt queue; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
G0
A2/0
S1/0
C6/1
A, E,
S1/S4
76/130
bit15
NS
NS
: Correctly Frame Received
: New Status.
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
: COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1
: Primitive or 6 bit word or AIS received
: New Primitive received twice consecutively. Case of S0=S1=0
S1
Nu
Nu
0
0
0
0
1
1
1
CFR =1, a receive frame is ended with a correct CRC. The end of the frame is located in the last
descriptor if several Descriptors.
Before writing the features of event in the external memory the Interrupt Controller reads the NS
bit:
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
6 bits received twice consecutively. Case of S0=1 S1=0.
S0
0
0
1
1
0
0
1
S1
S1
G0
0
1
0
1
0
1
0
S0=0
S0=1
Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4
Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI Multiplex 0 with-
out outgoing to DOUT4
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without outgo-
ing to DOUT5
AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16
bits) of the GCI Multiplex 0 (DOUT4) in transparent mode or not
AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16
bits) of the GCI Multiplex 1 (DOUT5) in transparent mode or not.
Reserved
G0
G0
A2
A2
A1
A1
bit8
A0
A0
Word stored in shared memory
bit7
Nu
Nu
Nu
Nu
C6
A
C5
E
C4
S1
C3
S2
C2
S3
bit 0
C1
S4