STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 64

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
C1/C0 : STATUS BITS
P0/1
F
NCRC : CRC NOT TRANSMITTED
CSMA : Carrier Sense Multiple Access with Contention Resolution
PEN
CF
VI.38 - HDLC Receive Command Register 2
64/130
bit15
CH4
CH3
: PROTOCOL BITS
: Flag
: CSMA PENALTY significant if CSMA = 1
: Common flag
F = 1; flags are transmitted between closing flag of current frame and opening flag of next frame.
F = 0; “1” are transmitted between closing flag of current frame and opening flag of next frame.
NCRC = 1, the CRC is not transmitted at the end of the frame.
NCRC =0, the CRC is transmitted at the end of the frame.
CSMA = 1, CB2 output and the Echo Bit EC2 are taken into account during this channel trans-
mission by the TxHDLC2.
CSMA = 0, CB2 output and the Echo Bit EC2 are defined by V11 (see “Time slot Assigner Data
Register 2 TADR2(56)
PEN = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count
(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the buffer descriptor related to the frame.
PEN = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count
(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the transmit descriptor related to the frame).
CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next
frame is ready to be transmitted.
CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
C1
P1
0
0
1
1
0
0
1
1
CH2
C0
P0
0
1
0
1
0
1
0
1
CH1
ABORT; the microprocessor has written ABORT or the transmitted frame has been aborted
by the HDLC Controller2 and it waits new command such as START or CONTINUE.
START; the microprocessor has written START.The HDLC Controller2 has not taken into ac-
count the command yet.
CONTINUE; the HDLC Controller2 has taken into account the command START.
TX DMA Controller is transferring frames.
CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already transmitted.
HDLC
Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken
into account.
Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not
taken into account.
Reserved
CH0 READ AR21 AR20 AR11 AR10 CRC
H
”).
STATUS BITS read by the microprocessor
After reset (0000)
bit8
Transmission Mode
bit7
H
FM
P1
P0
HRCR2 (5A)
C1
bit0
C0
H