STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 75

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VII.4 - Receive & Transmit HDLC Frame Interrupt
This word is located in the HDLC interrupt queue; IQSR Register indicates the size of this HDLC interrupt
queue located in the external memory.
NS
A5
Transmitter
Tx
A4/0
RRLF : Ready to Repeat Last Frame
EOQ : End of Queue
HALT : The Transmit DMA Controller has received HALT from the microprocessor; it is waiting “Contin-
BE
CFT
Receiver
Tx
A4/0
ERF
EOQ : End of Queue
HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the
BF
bit15
NS
A5
: New Status.
: 32 HDLC controller
: Tx = 1, Transmitter
: Tx HDLC Channel 0 to 31
: Buffer empty
: Correctly Frame Transmitted
: Tx = 0, Receiver
: Rx HDLC Channel 0 to 31
: Error detected on Received Frame
: Buffer Filled
Before writing the features of event in the external memory the Interrupt Controller reads the NS
bit:
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame
which has been transmitted or received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
A5 = 1, Second 32 HDLC controller (connected to Dout6/ Din6 of the switching matrix).
A5 = 0, First 32 HDLC controller (connected to Dout7/ Din7 of the switching matrix).
In consequence of event such as Abort Command HDLC, Controller is waiting Start or Continue
The Transmit DMA Controller has encountered the current Transmit Descriptor with EOQ at “1”.
DMA Controller is waiting “Continue” from microprocessor.
ue” from microprocessor.
If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMA Controller puts BE at “1” when the
buffer has been emptied.
A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is
at ‘1’. CFT is located in the last descriptor if several descriptors are used to define a frame.
An error such as CRC not correct, Abort, Overflow has been detected.
The Receive DMA Controller has encountered the current receive Descriptor with EOQ at “1”.
DMA Controller is waiting “Continue” from microprocessor.
microprocessor; it is waiting “Continue” or “Start” from the microprocessor.
If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has
filled the current buffer with data from the received frame.
Tx
A4
A3
A2
A1
A0
bit8
0
bit7
0
0
CFT/CFR
BE/BF
HALT
EOQ
STLC5466
RRLF/ERF
bit 0
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