92HD81B1C5NLGXUAX Integrated Device Technology (Idt), 92HD81B1C5NLGXUAX Datasheet - Page 68

• Manufacturer Part Number: 92HD81B1C5NLGXUAX
• Description: Audio Codec 2ADC / 2DAC 24-Bit 48-Pin VFQFPN EP Tray
• Manufacturer: Integrated Device Technology (Idt)
• Type: General Purposer

Specifications of 92HD81B1C5NLGXUAX

• Package: 48VFQFPN EP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /2 DAC
• Sampling Rate: 192 KSPS
• Number Of Dac Outputs: 8
• Number Of Dacs: 2
• Operating Supply Voltage: 1.5|1.8|3.3|4|4.75|5 V

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rsvd
Data2
Data1
Data0
Field Name
Rsvd
Mask2
Mask1
Reg
Get
Set
7.4.12. AFG (NID = 01h): GPIOEn
Byte 4 (Bits 31:24)
Bits
31:3
Reserved.
2
Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
1
Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
0
Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
Bits
31:3
Reserved.
2
Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
1
Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Byte 3 (Bits 23:16)
R/W
R
RW
RW
RW
R/W
R
RW
RW
F1600h
Default
00000000h
0h
0h
0h
Default
00000000h
0h
0h
68
Byte 2 (Bits 15:8)
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
92HD81
Byte 1 (Bits 7:0)
716h
PC AUDIO
V 0.987 11/09