MT46V128M8P-6T:A Micron Technology Inc, MT46V128M8P-6T:A Datasheet - Page 22

• Manufacturer Part Number: MT46V128M8P-6T:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V128M8P-6T:A

• Density: 1 Gb
• Maximum Clock Rate: 333 MHz
• Package: 66TSOP
• Address Bus Width: 16 Bit
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 128Mx8
• Address Bus: 16b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 230mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising - hold time
DQS falling edge to CK rising - setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command
interva
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to V
DQS write preamble
DQS write preamble setup time
Electrical Characteristics and Recommended AC Operating Conditions (-6T)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ T
A
≤ +70°C; V
SS
DD
Q = +2.5V ±0.2V, V
CL = 2.5
CL = 2
1Gb
1Gb
1Gb
DD
= +2.5V ±0.2V
22
Symbol
t
t
t
CK (2.5)
t
t
DQSCK
t
t
t
t
t
WPRES
t
t
t
t
CK (2)
DQSH
DQSQ
WPRE
t
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
t
t
RPRE
MRD
REFC
RPST
t
t
t
t
DSH
t
t
QHS
RCD
REFI
RRD
VTD
t
t
t
IPW
RAP
RAS
t
t
DSS
t
t
t
RFC
t
DH
QH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AC
CH
IH
IH
DS
HP
HZ
IS
IS
RC
CL
LZ
RP
Electrical Specifications – DC and AC
F
S
F
S
–0.70
t
t
Min
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.45
t
0.75
0.75
0.25
–0.6
–0.7
QHS
120
1Gb: x4, x8, x16 DDR SDRAM
HP -
t
7.5
0.2
0.2
CH,
0.8
2.2
0.8
0.9
0.4
12
15
42
60
15
15
12
CL
6
–
0
0
–
–
–
–
-6T (TSOP)
70,000
+0.70
Max
0.55
0.55
+0.6
0.45
1.25
+0.7
0.55
70.3
7.8
1.1
0.6
13
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
©2003 Micron Technology, Inc. All rights reserved.
Units
t
t
t
t
t
t
t
t
t
t
ns
CK
ns
ns
CK
ns
ns
ns
CK
CK
ns
CK
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
CK
CK
ns
ns
CK
ns
Notes
46, 52
46, 52
27, 32
26, 27
27, 32
19, 43
19, 43
26, 27
36, 54
21, 22
31
31
32
35
15
15
24
24
50
44
44