MT46V128M8P-6T:A Micron Technology Inc, MT46V128M8P-6T:A Datasheet - Page 54

DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray

MT46V128M8P-6T:A

Manufacturer Part Number
MT46V128M8P-6T:A
Description
DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46V128M8P-6T:A

Density
1 Gb
Maximum Clock Rate
333 MHz
Package
66TSOP
Address Bus Width
16 Bit
Operating Supply Voltage
2.5 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (128M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Package / Case
66-TSOP
Organization
128Mx8
Address Bus
16b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
230mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 26:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Consecutive READ Bursts
Notes:
Command
Command
Command
Address
Address
Address
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order follow-
5. Shown with nominal
6. Example applies only when READ commands are issued to same device.
the first).
ing DO b.
Bank,
READ
Col n
Bank,
READ
Bank,
READ
Col n
Col n
T0
T0
T0
CL = 2
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
AC,
CL = 3
t
DQSCK, and
54
Bank,
Bank,
Bank,
READ
Col b
Col b
Col b
READ
READ
T2
T2
T2
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
T2n
T2n
DO
n
T3
NOP
NOP
NOP
T3
T3
DO
1Gb: x4, x8, x16 DDR SDRAM
n
T3n
T3n
T3n
Transitioning Data
T4
NOP
T4
T4
NOP
NOP
©2003 Micron Technology, Inc. All rights reserved.
DO
b
T4n
T4n
T4n
DO
b
Operations
T5
T5
T5
NOP
NOP
NOP
DO
Don’t Care
b
T5n
T5n
T5n

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