XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 178
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XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 5: Configurable Logic Blocks (CLBs)
178
Look-Up Table (LUT)
Storage Elements
The function generators in Virtex-5 FPGAs are implemented as six-input look-up tables
(LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent
outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The
function generators can implement any arbitrarily defined six-input Boolean function.
Each function generator can also implement two arbitrarily defined five-input Boolean
functions, as long as these two functions share common inputs. Only the O6 output of the
function generator is used when a six-input function is implemented. Both O5 and O6 are
used for each of the five-input function generators implemented. In this case, A6 is driven
High by the software. The propagation delay through a LUT is independent of the function
implemented, or whether one six-input or two five-input generators are implemented.
Signals from the function generators can exit the slice (through A, B, C, D output for O6 or
AMUX, BMUX, CMUX, DMUX output for O5), enter the XOR dedicated gate from an O6
output (see
(see
O6 output (see
to F7AMUX/F7BMUX from O6 output.
In addition to the basic LUTs, slices contain three multiplexers (F7AMUX, F7BMUX, and
F8MUX). These multiplexers are used to combine up to four function generators to provide
any function of seven or eight inputs in a slice. F7AMUX and F7BMUX are used to
generate seven input functions from LUTs A and B, or C and D, while F8MUX is used to
combine all LUTs to generate eight input functions. Functions with more than eight inputs
can be implemented using multiple slices. There are no direct connections between slices
to form function generators greater than eight inputs within a CLB or between slices.
The storage elements in a slice can be configured as either edge-triggered D-type flip-flops
or level-sensitive latches. The D input can be driven directly by a LUT output via
AFFMUX, BFFMUX, CFFMUX or DFFMUX, or by the BYPASS slice inputs bypassing the
function generators via AX, BX, CX, or DX input. When configured as a latch, the latch is
transparent when the CLK is Low.
The control signals clock (CK), clock enable (CE), set/reset (SR), and reverse (REV) are
common to all storage elements in one slice. When one flip-flop in a slice has SR or CE
enabled, the other flip-flops used in the slice will also have SR or CE enabled by the
common signal. Only the CLK signal has independent polarity. Any inverter placed on the
clock signal is automatically absorbed. The CE, SR, and REV signals are active High. All
flip-flop and latch primitives have CE and non-CE versions.
The SR signal forces the storage element into the state specified by the attribute SRHIGH or
SRLOW. SRHIGH forces a logic High at the storage element output when SR is asserted,
while SRLOW forces a logic Low at the storage element output. When SR is used, an
optional second input (DX) forces the storage element output into the opposite state via the
REV pin. The reset condition is predominant over the set condition (see
Table 5-3
SRLOW or SRHIGH is used.
Table 5-3: Truth Table when SRLOW is Used (Default Condition)
Fast Lookahead Carry
and
Fast Lookahead Carry
SR
Table 5-4
0
0
Fast Lookahead Carry
provide truth tables for SR and REV depending on whether
www.xilinx.com
Logic), enter the select line of the carry-logic multiplexer from
Logic), enter the carry-logic chain from an O5 output
Logic), feed the D input of the storage element, or go
REV
0
1
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
No Logic Change
Function
Figure
1
5-5).
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