XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 308
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 308 of 385
- Download datasheet (14Mb)
Chapter 6: SelectIO Resources
308
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
1.5V
LVCMOS15_2_slow
LVCMOS15_4_slow
LVCMOS15_6_slow
LVCMOS15_8_slow
LVCMOS15_12_slow
LVCMOS15_16_slow
LVCMOS15_2_fast
LVCMOS15_4_fast
LVCMOS15_6_fast
LVCMOS15_8_fast
LVCMOS15_12_fast
LVCMOS15_16_fast
LVDCI_15 50 Ω
HSTL_I_15
HSTL_I_15_DCI
HSTL_II_15
HSTL_II_15_DCI
HSTL_III_15
HSTL_III_15_DCI
HSTL_IV_15
HSTL_IV_15_DCI
HSLVDCI_15 50 Ω
DIFF_HSTL_I_15
DIFF_HSTL_I_15_DCI
DIFF_HSTL_II_15
DIFF_HSTL_II_15_DCI
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
12
12
20
20
20
20
20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
25
25
40
40
40
40
40
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