XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 50
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XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 2: Clock Management Technology
DCM Primitives
50
DCM_BASE Primitive
The DCM primitives DCM_BASE and DCM_ADV are shown in
X-Ref Target - Figure 2-2
The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE.
DCM_BASE primitive.
Table 2-2: DCM_BASE Primitive
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Available Ports
CLKIN
CLKFB
RST
DCM_BASE
www.xilinx.com
CLKFX180
CLK2X180
LOCKED
CLKIN, CLKFB
RST
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
Figure 2-2: DCM Primitives
CLK0
Table 2-2
CLKIN
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
Port Names
DCM_ADV
lists the available ports in the
CLKFX180
CLK2X180
PSDONE
LOCKED
DO[15:0]
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
Figure
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DRDY
CLK0
ug190_2_02_042706
2-2.
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