XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 309
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 309 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
1.8V
LVCMOS18_2_slow
LVCMOS18_4_slow
LVCMOS18_6_slow
LVCMOS18_8_slow
LVCMOS18_12_slow
LVCMOS18_16_slow
LVCMOS18_2_fast
LVCMOS18_4_fast
LVCMOS18_6_fast
LVCMOS18_8_fast
LVCMOS18_12_fast
LVCMOS18_16_fast
LVDCI_18 50 Ω
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
HSTL_III_18
HSTL_III_DCI_18
HSTL_IV_18
HSTL_IV_DCI_18
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL18_II_DCI
HSLVDCI_18 50 Ω
DIFF_HSTL_I_18
DIFF_HSTL_I_DCI_18
DIFF_HSTL_II_18
DIFF_HSTL_II_DCI_18
DIFF_SSTL18_I
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II_DCI
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
Simultaneous Switching Output Limits
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
17
17
10
10
20
20
20
20
20
20
20
20
20
20
20
20
20
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
35
35
20
20
40
40
40
40
40
40
40
40
40
40
40
40
40
309
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