XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 88
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 88 of 385
- Download datasheet (14Mb)
Chapter 2: Clock Management Technology
Legacy Support
88
The Virtex-5 FPGA DCMs (DCM_BASE and DCM_ADV) have exactly the same port
names as the Virtex-4 FPGA DCMs. However, the DRP address mapping has changed.
Refer to the Virtex-5 FPGA Configuration Guide for more information.
The Virtex-5 device supports the Virtex-II family and Virtex-II Pro FPGA DCM primitives.
The mapping of Virtex-II or Virtex-II Pro FPGA DCMs to Virtex-5 FPGA DCM_ADVs are
as follows:
•
•
•
CLKIN, CLKFB, PSCLK, PSINDEC, PSEN, RST, CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKFX, CLKFX180, CLKDV, PSDONE, LOCKED of Virtex-5
FPGA primitives (DCM_BASE/DCM_ADV) map to the same corresponding pins of a
Virtex-II or Virtex-II Pro FPGA DCM.
Dynamic reconfiguration pins of Virtex-5 FPGA DCM_ADV are not accessible when a
Virtex-II or Virtex-II Pro FPGA DCM is used, except for DO[15:0].
DO[7:0] pins of Virtex-5 FPGA DCM_ADV map to Status[7:0] of the Virtex-II or
Virtex-II Pro FPGA DCMs. DO[15:8] of DCM_ADV are not available when using
Virtex-II or Virtex-II Pro FPGA DCMs.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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