OCX256LTB792 Fairchild Semiconductor, OCX256LTB792 Datasheet
OCX256LTB792
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OCX256LTB792 Summary of contents
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... SRAM-based, in-system programmable LVDS I/O (OCX256L) and LVPECL I/O (OCX256P) versions Ordering Code: Order Number Package Number OCX256LTB792 BGA792A 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square OCX256PTB792 BGA792A 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, ...
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IN[127:0] Input Buffers 7 RCA[6:0] 7 RCB[6:0] 4 RCI[3:0] RapidConfigure Signals RCO[4:0] 5 RC_CLK RC_EN UPDATE FIGURE 1. OCX256 Functional Block Diagram Introduction The OCX256 is a differential crosspoint-switching device. The main functional block of the device is a ...
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Introduction (Continued) Input and Output Buffers All of the input buffers are differential inputs with flow- through mode. The output buffers are programmable for either flow-through or registered mode. Figure 3 shows the Input FIGURE 3. Input and Output Buffer ...
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Introduction (Continued) Neighboring Output Port as a Clock Source A physically adjacent port can be used as a clock source for an output port configured in registered mode. These outputs are grouped in pairs such that the signal being switched ...
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Introduction (Continued) TABLE 3. RapidConfigure Programming Instructions RCI[3:0] RCA[6:0] RCB[6:0] RCO[4:0] 0000 0001 0010 X X 0011 X Input Port Address 0100 Output Port Data Address 0101 Cycle 1 Output Port Input Port X Address Address Cycle ...
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Introduction (Continued) TABLE 4. RCO[4:0] Readback Pin Assignment RCO[4:0] Readback Location O4 Crosspoint O3 Output Buffer O2 Output Buffer O1, O0 Output Buffer TABLE 5. Programming an Output Buffer using RapidConfigure RCB[6:0] ...
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Introduction (Continued) Mode Control Register Configuration The OCX256 contains a single bit Mode Control Register used to store user flags for RapidConfigure Enable (RCE). These are required for proper functioning of the device. The contents of this register can be ...
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Introduction (Continued) I [3: ...
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Introduction (Continued) TABLE 9. JTAG Instructions (Continued) I [3: ...
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Introduction (Continued) TABLE 11. Number of JTAG Cycles and Configuration Time JTAG Reset Sequence (TMS = “11111”) Enable or Disable RapidConfigure Change Attributes of ONE Output Port Change Attributes of ALL Output Ports Reset JTAG Controller + Reset ALL Output ...
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Pin Description TABLE 13. OCX256 Pin Description Pin Name Number of Pins INPP[127:0] 128 INN[127:0] 128 OUTP[127:0] 128 OUTN[127:0] 128 CLKP 1 CLKN HW_RST 1 UPDATE 1 RCA[6:0] 7 RCB[6:0] 7 RCO[4:0] 5 RCI[3:0] 4 RC_CLK 1 ...
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Differential I/O Standards The OCX256 supports the two most popular differential signaling standards: Low Voltage Differential Signaling (LVDS) and Low Voltage Positive Emitter Coupled Logic (LVPECL). LVDS is typically used in communication systems as high speed, low noise point-to-point links. ...
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Absolute Maximum Ratings Supply Voltage (Core) V .CORE DD Supply Voltage (Inputs) V .IN DD Supply Voltage (Differential Outputs) V .PAD DD Input Voltage V (Note 5)(Note 6) IN Junction Temperature T J Storage Temperature T -65°C to +150°C STG ...
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OCX256L (LVDS) DC Electrical Specifications Symbol DC Parameter V Output High Voltage for OUTP and OUTN OH V Output Low Voltage for OUTP and OUTN OL V Differential Output Voltage (Note 13) OUT_DIFF V Output Common-Mode Voltage OUT_COM V Differential ...
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Timing Diagrams For the purpose of clarity, the timing diagrams within this datasheet are conceptual representations only and do not show actual circuit implementation. FIGURE 9. Registered Output Mode Timing FIGURE 10. Flow-Through Mode Timing FIGURE 11. Output Enable Timing ...
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Timing Diagrams (Continued) RC_CLK RCA/RCB Address, Instruction RC_EN FIGURE 13. Rapid Configure Write Cycle RC_CLK RCA/RCB Address, Instruction RC_EN FIGURE 14. Rapid Configure Read Cycle www.fairchildsemi.com W+_RC W-_RC t t S_RC H_RC t t ...
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Timing Diagrams (Continued) FIGURE 16. Typical Performance at 667 Mb/s with PRBS Data FIGURE 15. JTAG Timing 17 Preliminary www.fairchildsemi.com ...
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Package and Pinout Vss Vss OUT01P Vss OUT09N Vss A Vss Vss OUT03N OUT06N OUT11N OUT14P V .PAD Vss Vss V .PAD OUT04N OUT08P Vss ...
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Package and Pinout (Continued) TABLE 14. OCX256 Pinout By Ball Sequence Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name ...
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Package and Pinout (Continued) Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name IN121N SS G2 IN123N H2 IN122P G3 IN124P H3 ...
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Package and Pinout (Continued) Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name AE1 V AF1 IN82P AG1 SS AE2 IN84N AF2 IN81N AG2 AE3 ...
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Package and Pinout (Continued) Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name AP1 IN65N AR1 V SS AP2 IN65P AR2 V .IN DD AP3 ...
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Package and Pinout (Continued) TABLE 15. OCX256 Pinout By Ball Name Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # CLKN F35 IN21P CLKP E37 IN22N HW_RST E6 IN22P ...
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Package and Pinout (Continued) Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name Ball # IN113P M5 OUT07P IN114N L2 OUT07N IN114P L1 OUT08P IN115N L4 OUT08N IN115P L3 OUT09P IN116N ...
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Package and Pinout (Continued) Ball Name Ball # Ball Name Ball # Ball Name Ball # Ball Name OUT101P AV17 OUT124N OUT101N AT18 OUT125P OUT102P AT17 OUT125N OUT102N AU17 OUT126P OUT103P AP17 OUT126N OUT103N AR17 OUT127P OUT104P AV16 OUT127N OUT104N ...
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Package and Pinout (Continued) Ball Name Ball # Ball Name Ball # Vss B37 B38 B39 ...
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Package and Pinout (Continued) Power Consumption Chip power consists of three integral elements (refer to Table 18): 1. Input Power—This element has two components: a steady state component that is always ON, and a component that is based on the ...
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Package and Pinout (Continued) Glossary Clock: A single differential input used to gate data into reg- isters in the Output Buffer. The input serves all outputs of the OCX. The neighbor input can also be used as a register clock. ...
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Physical Dimensions inches (millimeters) unless otherwise noted 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...