OCX256LTB792 Fairchild Semiconductor, OCX256LTB792 Datasheet - Page 2

• Manufacturer Part Number: OCX256LTB792
• Manufacturer: Fairchild Semiconductor

Specifications of OCX256LTB792

• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Mounting: Surface Mount
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

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Introduction
The OCX256 is a differential crosspoint-switching device.
The main functional block of the device is a Switch Matrix
as shown in Figure 1. The Switch Matrix is a x-y structure
supporting an input-to-output data flow. Figure 2 shows a
conceptual view of the switch matrix with inputs connected
to the horizontal trace and outputs to the vertical trace.
Connections between vertical and horizontal lines are
The Active SRAM cells are responsible for establishing
connections in the switch matrix by turning on the intercon-
nect circuit, while the Loading SRAM cell can be used to
store a second configuration that can be transferred to the
Active SRAM cell at a later time. The two SRAM cells are
arranged so that a double buffered scheme can be
employed. Through the use of an internal signal (generated
automatically during a programming cycle) it is possible to
store a second configuration map in the Loading SRAM
while the Active SRAM maintains its present connection
status. When the UPDATE signal is asserted LOW (Active
LOW), the contents of the Loading SRAM cell are trans-
ferred to the Active SRAM cell and the switch matrix con-
nection is either made or broken.
RapidConfigure
Signals
IN[127:0]
RC_CLK
RCA[6:0]
RCB[6:0]
RCI[3:0]
RCO[4:0] 5
RC_EN
UPDATE
Data
256
Proprietary High-performance
7
4
7
Loading
SRAM
Cell
Buffering Circuit
FIGURE 1. OCX256 Functional Block Diagram
Buffers
Input
FIGURE 2. OCX256 Switch Matrix
UPDATE
SRAM
Active
Cell
Programming Logic
Configuration and
Switch Matrix
2
Crosspoint
128 x 128
implemented with a proprietary high-performance buffering
circuit. Signal path delays through the Switch Matrix are
very well balanced, resulting in predictable and uniform
pin-to-pin delays.
Note: For the purpose of clarity, the logic diagrams within this datasheet
are conceptual representations only and do not show actual circuit imple-
mentation.
The UPDATE signal can be used to control when the
switch matrix is reconfigured. For instance, as long as the
UPDATE signal is de-asserted (held HIGH), the Loading
SRAM cells for the entire switch matrix could be changed
without affecting the current configuration of the switch.
When the UPDATE signal is asserted LOW, the entire
switch matrix would be reconfigured simultaneously. If the
UPDATE signal is asserted continuously, all crosspoint pro-
gramming commands (generated by RapidConfigure or
JTAG programming cycles) will take effect immediately,
since the Loading SRAM cell’s contents will be transferred
directly to the Active SRAM cell.
Output
Buffers
256
OUT[127:0]
2
TCK
TMS
TDI
TDO
TRST
HW_RST
CLK
OE
Preliminary
Signals
JTAG