OCX256LTB792 Fairchild Semiconductor, OCX256LTB792 Datasheet - Page 3

• Manufacturer Part Number: OCX256LTB792
• Manufacturer: Fairchild Semiconductor

Specifications of OCX256LTB792

• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Mounting: Surface Mount
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

Introduction
Input and Output Buffers
All of the input buffers are differential inputs with flow-
through mode. The output buffers are programmable for
either flow-through or registered mode. Figure 3 shows the
Input and Output Port Function Mode
The following legend describes the various modes of the
Input and Output Ports and the specification used by the
OCXPro Software.
Broadcast Mode
The OCX256 has a special Broadcast Mode which con-
nects any input to all outputs without performance degra-
dation. The input is selected using RapidConfigure or
JTAG and disconnects all other inputs. The Global Update
pin (UPDATE) must be held high during Broadcast Mode.
Asserting the UPDATE pin returns the array to the previous
program condition.
Output Buffer Configuration
Every output port of the OCX256 can be configured as
either a flow-through or registered output. In registered
mode there are two clock sources that are available:
• Global Clock
• Next Neighbor
Additionally, there are output control signals.
Px
Ax
CLK
Ax
Px
Symbol
D
OE
Q
OE
Ax
Ax
Px
(Continued)
Input
Px
Registered Output The internal signal on the Switch Matrix line is registered by
TABLE 1. Summary for Programmable I/O Attributes for OCX256
No Connect
Output
Input
FIGURE 3. Input and Output Buffer Configuration
The external signal is buffered from the Input Port pin to the
corresponding Switch Matrix line.
The internal signal is buffered from the corresponding Switch
Matrix line to the Output Port pin. In this mode an optional
output enable (OE) can be selected. The default state is logic
high with enable set to ON.
an edge-triggered register within the Output Port. A clock
source is required in this mode. An output enable (OE) is
available but not required.
In this mode, the output Port pin is isolated from the Switch
Matrix
Switch
Matrix
Neighbor
Next
CLK
I/O Port Function
3
Select
basic block diagram of the input and output blocks with the
sources for the output control signals (OE and CLK). The
control signals are explained in more details in the follow-
ing sections
Legend:
Output Control Signals
Every output port of the OCX has a global Output Enable
signal (OE). All output buffers have output enables that
have programmable polarity and are individually config-
urable.
Additionally each output can be permanently enabled
(always ON) or disabled (always OFF) which is useful for
applications which need to 3-STATE outputs (for example
when using multiple chips in expansion mode) or for power
saving in designs that do not need to use all the outputs
available.
Two control bits are used to control the function of the out-
put enable function as described in Table 5.
Clock
Ax–Switch Matrix Signal
Px–Port Signal
OE–Output Enable (Active LOW)
CLK–Clock
D
Q
Output Mode
Select
OE
Output
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Preliminary
Mnemonic
RO
OP
NC
IN