KS8993F A5 Micrel Inc, KS8993F A5 Datasheet - Page 3

• Manufacturer Part Number: KS8993F A5
• Manufacturer: Micrel Inc

Specifications of KS8993F A5

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

KS8993F
Revision History
August 26, 2004
Revision
P0
P1
P2
P3
P4
P5
1.0
Date
1/14/03
2/11/03
4/1/03
12/4/03
3/11/04
3/23/04
8/26/04
Summary of Changes
Preliminary Information
Added separate Link and activity on port 1 and port 2’s LED (pin #20, pin #23,
Added disable auto MDI/MDIX (pin #28)
Added select of MDI and MDIX (pin #29)
Updated register information
Started overhaul of datasheet.
Updated strap option definition for pin #85.
Renamed supply voltages and ground references to match schematics.
Corrected Remote Loop back path.
Updated MC registers descriptions.
Changed 3.3V voltage pins to (3.3V or 2.5V).
Completed overhaul of datasheet.
Revised datasheet format.
Updated KS8993F block diagram.
Updated Feature Highlights.
Updated MC registers descriptions.
Updated Electrical Characteristics (Vih, Vil, Voh, Vol).
Updated MC loop back description in pin #19 and register 11 bits[3:2], and path in
Updated flow diagram for Destination Address resolution flowchart, stage2.
Changed S10 status bit from RO to R/W in register 81 bit[2].
Added KS8993FL to General Description (page 1) and Functional Description
Updated pin description for pin 22 to the following:
Improved/clarified pin description.
Updated PPM spec for 25 MHz crystal/oscillator.
Improved/clarified pin description for P1LCRCD (pin 18), P2MDIX (pin 29) and
Corrected aging time.
Removed loop back support from MIIM and Port Control Registers, so that there is no
Updated HWPOVR description in section 2.2.5.
Corrected default definition for FEF in section 2.3.6, and MIIM and Port Control
Added register note to indicate port sniffing is not supported if the unicast packets can
Improved/clarified switch/PHY registers descriptions for Force MDIX and CRC drop.
Improved/clarified MC registers descriptions for Remote Command (registers 74, 75,
Added register note to set Register 85: My Model Info (1) to values of 0x22, 0x26,
Updated MIB counters descriptions to indicate counter overflow must be tracked by
pin #25).
loop back diagram.
Overview (section 2.1).
VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD.
VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the
confusion with MC loop back which is used exclusively in KS8993F application.
Registers.
cross VLAN boundary bit is set.
76), My Status (registers 80, 81) and LNK Partner Status (registers 88, 89).
0x2A and 0x2E if the Remote Command feature is used.
application.
MDIO (pin 95).
- 3 -
KS8993FL’s input power pins: VDDAP (pin 63),
VDDC (pins 91, 123) and VDDA (pins 38, 43, 57).
Revision 1.0
Micrel