KS8993F A5 Micrel Inc, KS8993F A5 Datasheet - Page 61

• Manufacturer Part Number: KS8993F A5
• Manufacturer: Micrel Inc

Specifications of KS8993F A5

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

KS8993F
Register 27 (0x1B): Port 1 Control 11
NOTE: Port Control Registers 12 and 13, and Port Status Register 0 contents can also be
Register 28 (0x1C): Port 1 Control 12
August 26, 2004
Bit
7
6
5
4
3
2
1
0
Bit
7
Register 43 (0x2B): Port 2 Control 11
Register 59 (0x3B): Port 3 Control 11
accessed with the MIIM (MDC/MDIO) interface via the standard MIIM registers.
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Reserved, not applied to port 3
Name
Receive
differential
priority rate
control
Low priority
receive rate
control
enable
High priority
receive rate
control
enable
Low priority
receive rate
flow control
enable
High priority
receive rate
flow control
enable
Transmit
differential
priority rate
control
Low priority
transmit rate
control
enable
High priority
transmit rate
control
enable
Name
Auto
Negotiation
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
= 1, If bit 6 is also ‘1’, this will enable receive rate control for
high
= 0, receive rate control will be based on the low priority rate
= 1, enable port’s low priority receive rate control feature
= 0, disable port’s low priority receive rate control feature
= 1, If bit 7 is also ‘1’, this will enable the
priority receive rate control feature. If bit 7 is a ‘0’ and bit 6 is
a
= 0, disable port’s high priority receive rate control feature
= 1, flow control may be asserted if the port’s low priority
= 0, flow control is not asserted if the port’s low priority receive
= 1, flow control may be asserted if the port’s high priority
= 0, flow control is not asserted if the port’s high priority
= 1, will do transmit rate control on both high and low priority
= 0, will do transmit rate control on any packets. The rate
= 1, enable the port’s low priority transmit rate control feature
= 0, disable the port’s low priority transmit rate control feature
= 1, enable the port’s high priority transmit rate control feature
= 0, disable the port’s high priority transmit rate control feature
Description
= 0, disable auto negotiation, speed and
decided
= 1, auto negotiation is ON
this port on low priority packets at the low priority rate. If
bit 5 is also ‘1’, this will enable receive rate control on
for all packets on this port.
‘1’, all receive packets on this port will be rate controlled
at the low priority rate.
receive rate is exceeded
rate is exceeded
receive rate is exceeded. (to use this, differential receive
rate control must be ON)
receive rate is exceeded.
packets based on the rate counters defined by the high
and low priority packets respectively.
counters defined in low priority will be used.
priority packets at the high priority rate.
by bit 6 and 5 of the same register.
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port’s high
duplex are
Default
0
0
0
0
0
0
0
0
Default
For port 1,
P1ANEN pin
value during
reset
For port 2,
Revision 1.0
Micrel