82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 47

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
pared if the Sa6SYN bit is ‘1’. If a matched code is detected, the
corresponding indication bit in the Sa6 Code Indication register will be
set.
3.8.2.4
is detected with the indication in the V52LINKV bit. This detection is dis-
abled when the Basic Frame is out of synchronization.
3.8.2.5
When there are conditions meeting the interrupt sources, the corre-
Functional Description
Table 20: Interrupt Source In E1 Frame Processor
In CRC to Non-CRC inter-working.
It is out of Basic frame synchronization.
It is out of CRC multi-frame synchronization.
It is out of CAS Signaling multi-frame synchronization.
The new-found Basic frame alignment pattern position differs from the previous one.
FAS/NFAS Bit/Pattern Error occurs.
CRC Multi-Frame Alignment Pattern Error occurs.
CAS Signaling Multi-Frame Alignment Pattern Error occurs.
CRC-4 Error occurs.
Offline Basic frame search indication.
Far End Block Error occurs.
Continuous RAI & FEBE Error occurs.
Continuous FEBE Error occurs.
At the first bit of each CRC Multi-Frame.
At the first bit of each CRC Sub Multi-Frame.
At the first bit of each CAS Signaling Multi-Frame.
There is change in the corresponding SaX[1:4] bits. The ‘X’ is from 4 through 8.
Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords are matched
with 0x888, 0xAAA, 0xCCC, 0xEEE or 0xFFF.
NT FEBE Error occurs.
NT CRC Error occurs.
2 out of 3 sliding Sa7 bits are received as logic 0.
The V5.2 link ID signal, i.e., 2 out of 3 sliding Sa7 bits being logic 0,
The interrupt sources in this block are summarized in Table 20.
V5.2 Link
Interrupt Summary
Sources
47
sponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding Sta-
tus Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by a write
signal. A ‘1’ in the Status Interrupt Indication bit means an interrupt
occurred. The interrupt will be reported by the INT pin if its Status Inter-
rupt Enable bit is ‘1’.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Status Bit
C2NCIWV
V52LINKV
RAICRCV
OOCMFV
OOSMFV
CFEBEV
OOOFV
OOFV
-
-
-
-
-
-
-
-
-
-
-
-
-
Sa4I / Sa5I / Sa6I / Sa7I /
Interrupt Indication Bit
C2NCIWI
V52LINKI
OOCMFI
RAICRCI
ICSMFPI
OOSMFI
CMFERI
SMFERI
TCRCEI
CFEBEI
ICMFPI
Sa6SCI
TFEBEI
OOOFI
ISMFPI
CRCEI
COFAI
FEBEI
OOFI
FERI
Sa8I
Sa4E / Sa5E / Sa6E /
Interrupt Enable Bit
August 20, 2009
Sa7E / Sa8E
C2NCIWE
V52LINKE
RAICRCE
ICSMFPE
OOCMFE
OOSMFE
CMFERE
SMFERE
TCRCEE
CFEBEE
ICMFPE
Sa6SCE
TFEBEE
ISMFPE
CRCEE
OOOFE
COFAE
FEBEE
OOFE
FERE