82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 69
82P2282PF
Manufacturer Part Number
82P2282PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2282PF.pdf
(381 pages)
Specifications of 82P2282PF
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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IDT82P2282
BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame output on the RSDn/MRSD pin will delay ‘N’
clock cycles to the framing pulse on the RSFSn/MRSFS pin. (Here ‘N’ is
defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and the
TSOFF[6:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSD pin will delay ‘8 x M’ clock cycles to the framing pulse
on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
Functional Description
The bit offset and channel offset are configured when the
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
Receive Clock Master mode:
Receive Clock Slave mode / Receive Multiplexed mode:
RSDn / MRSD
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
RSFSn / MRSFS
RSCKn / MRSCK
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path
FE = 1, DE = 0
FE = 0, DE = 1
F-bit of CH1 (T1/J1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
69
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSD pin will delay ‘2 x N’ clock cycles to the framing pulse
on the RSFSn/MRSFS pin. (Here ‘N’ is defined by the BOFF[2:0] bits.)
When the CMS bit is ‘1’ (i.e., in double clock mode) and the TSOFF[6:0]
bits are set, the start of the corresponding frame output on the RSDn/
MRSD pin will delay ‘16 x M’ clock cycles to the framing pulse on the
RSFSn/MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
August 20, 2009
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