TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 4

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
DS3F
DATA SHEET
TXC-03401B
BLOCK DIAGRAM DESCRIPTION
Figure 1 shows the block diagram of the DS3F device.
The DS3F is designed to operate in both "Normal" (N) and "Extended-features" (E) modes of operation. In the
Normal mode, the device emulates the TranSwitch TXC-03401 DS3F device. In the Extended-features mode,
all the additional capabilities described in this Data Sheet are available. Technical Bulletin TB-511 describes
the differences between the TXC-03401 and the TXC-03401B (document number TXC-03401-TB1). Either
mode of operation can be selected by setting control bit EMODE in the memory map. Two input pins
(FORCECP/CVCNT and FORCEPP/EXZCNT) and one output pin (STUFD/HINT) can change their functions
according to the mode selected (N/E). Memory map addresses above 07H are effective only in the Extended-
features mode.
The DS3F receives a line side DS3 data signal (D3RD) and a clock signal (D3RC) from a line interface device
such as the TranSwitch ART/ARTE VLSI device (TXC-02020/02021) or DS3LIM-SN module (TXC-20153D or
TXC-20153G). The DS3 Frame Alignment Block performs DS3 frame alignment that will not lock to a false
framing pattern. There are internal 8-bit F- and M-bit error counters included in the Extended-features mode of
the framer to monitor errors. The DS3F also monitors the signal and the input clock for loss of signal (LOS), out
of frame (OOF), and loss of clock (LOC). A framing error (FE) output is provided to indicate when any of the 31
framing bits in the DS3 signal are in error.
The DS3 Interpreter Block performs P-bit and C-bit parity detection and error counting, receive AIS and idle
pattern detection, far end block error (FEBE) detection and error counting, far end alarm and control (FEAC)
code word detection of up to 4 different types, C-bit reception and X-bit reception. Serial interfaces are pro-
vided for the received X-bits and for 14 of the 21 C-bits. In the Extended-features mode, groups of the C-bits
can be set by writing to the memory map. The receive C-bit interface consists of a serial data signal (CRD),
clock signal (CRCK), framing pulse (CRF), and a data communication link clock signal (CRDCC). The clock
signal (CRCK) is gapped and is available only for clocking out C-bits C2 through C6, and C13 through C21.
The CRDCC clock signal is present only for C-bits C13, C14 and C15, which are assigned as a data communi-
cation channel when operating in the C-bit parity mode. In the Extended-features mode, the timing of the
CRDCC receive clock edges can be reversed by setting a control bit in the memory map.
When operating in the M13 mode, an interface (output pin STUFD) that indicates the state of the stuff opportu-
nity bit during each of the seven DS3 subframes and a clock signal (STUFC) are also provided. The Stuff Data
Status (STUFD) output pin is shared with the Hardware Interrupt (HINT) pin for the Extended-features mode.
The Hardware Interrupt output is used to the inform the microprocessor that a severe alarm condition has
occurred. The polarity of the Hardware Interrupt output is selectable by a control bit to meet the requirements
of the microprocessor's interrupt input pin. When a hardware interrupt does occur, it can be isolated to one of
up to up to eight different latched alarm types if they are enabled in the memory map.
The Output Block provides a bit-serial or a nibble-parallel interface for C-bit parity mode. The M13 mode uses
the bit-serial interface only. Note that since the sum of the payload and C-bits in a DS3 frame is not evenly
divisible by four, M13 nibble mode operation is not feasible. The interface type is selected by writing to a control
bit in the memory map (SER), and is common to the DS3F receive and transmit circuitry. The signals provided
for the bit-serial interface consist of a data signal (RDS), a clock signal (RCS), a receive clock gap signal
(RCG) and framing pulse (RFS). The nibble-parallel interface consists of the nibble data signal (RNIB3 through
RNIB0), a clock out signal (RCN), and a framing pulse output (RFN). The RNIB3 bit corresponds to the first bit
received in a four-bit serial bit stream segment.
In the transmit direction, the Input Block provides either a bit-serial or nibble-parallel interface. The bit-serial
interface consists of a data signal (XDS), clock signals (XCK and optionally XSC), and a framing pulse (XFSI).
The nibble-parallel interface consists of the nibble data (XNIB3 through XNIB0), a clock out signal (XCK), a
framing pulse (XFNO), and a nibble clock signal (XNC). The XNIB3 bit corresponds to the first bit transmitted.
The DS3 Send Block performs P-bit and C-bit parity generation, AIS and idle pattern generation, far end alarm
and control (single or double FEAC word) transmission, X-bit insertion, and C-bit insertion. For C-bit Parity
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TXC-03401B-MB
Ed. 6, June 2001