TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 9

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

RECEIVE TERMINAL SIDE INTERFACE
Symbol
RNIB3
RNIB2
RNIB1
RNIB0
RCS/
RDS/
RFS/
RCN
RCG
RFN
Pin No.
68-Pin
PLCC
Proprietary TranSwitch Corporation Information for use Solely by its Customers
31
34
39
40
41
42
32
Pin No.
80-Pin
TQFP
10
15
17
18
19
6
7
I/O/P
O
O
O
O
CMOS
CMOS
CMOS
Type
4mA
4mA
4mA
4mA
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TTL
DATA SHEET
Receive Framing Pulse Serial/Nibble Inter-
face: The framing pulse is active low for one clock
cycle (RCS/RCN), and is synchronous with the
first bit 1 in the DS3 frame. For the nibble inter-
face, the framing pulse is synchronous with nibble
1175.
Receive Clock Serial/Nibble Interface: Clock
used for clocking out the terminal side receive
serial and nibble data. This clock is derived from
the line side clock (D3RC). Data is clocked out of
the DS3F on falling edges of the RCS clock and
on rising edges of the RCN clock.
Receive Nibble/Serial Interface: Nibble data is
clocked out on rising edges of the nibble clock
(RCN). There are 1176 nibbles provided each
frame. The data and clock are stretched to
accommodate the 56 individual overhead bits
(first bit in the 85-bit group), which are not pro-
vided at the interface. The first bit received in a
nibble is present on RNIB3. The nibble interface is
operational in the C-bit parity operating mode
only. Serial data (RDS) consists of all the bits in
the frame (including the states of the overhead
bits), and is operational in either operating mode,
M13 or C-bit parity. Serial data is clocked out on
falling edges of the receive clock (RCS). For serial
data, a gapped clock signal is generated by the
receive circuitry and provided on the RNIB3 pin
when control bits SER and RGCEN are both set
to 1.
Receive Clock Gap Signal: The active low gap
signal is synchronous with each overhead bit in
the serial DS3 frame (first bit in the 85-bit group).
Name/Function
TXC-03401B
TXC-03401B-MB
Ed. 6, June 2001
DS3F