TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 44

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Address
12
13
14
7-0
7-0
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
FORCEFEBE
FORCECP Force C-Bit Parity Error: When the CVEN bit is set to 1, setting this bit to
CVEXZ15-
FORCEPP Force P-Bit Parity Error: When the CVEN bit is set to 1, setting this bit to
STFTGEN
TSTCNTR
CVEXZ7-
STFREN
CVEXZ0
CVEXZ8
Symbol
EXZEN
CVEN
Coding Violation 16-Bit Counter, low order byte: A 16-bit saturating
counter that counts the D3RC cycles for which CVCNT is high (and those
for which EXZCNT is low, if EXZEN is set to 1). These signals are outputs
from the ART (CV only) and ARTE devices and they are expected to be
related to the rising edge of D3RC. There are actually two counters, so that
when one counter is being read, the other counter is counting. A read
cycle for this register causes this switch to toggle, and the current count
data for the low order byte to be provided as output. Note: The counter
switch will toggle whenever ALE goes low while this address is selected,
so care should be taken if multiple DS3F devices are on the proc. I/O bus.
Coding Violation 16-Bit Counter, high order byte: A read cycle for this
register causes the high order count byte which corresponds to the most
recently read low order count byte from the register at Address 12H to be
provided as output and then this counter (all 16 bits) is cleared to 0000H. It
is therefore important to read the register at Address 12H first, followed by
a read of this register, to insure that a correct count is obtained.
Stuff Receive Enable: When set to 1, the RCG output of the receive data
circuitry will include the stuff bit locations if 2 out of 3 C-bits in that sub-
frame are set to 1, when operating in M13 mode and Serial mode.
Stuff Timing Generator Enable: When set to 1, the TCG output of the
timing generator will include the stuff bit locations when operating in M13
mode and Serial mode.
Force FEBE Error: When the CVEN bit is set to 1, setting this bit to 1 will
generate and transmit a far end block error (FEBE) by setting C10, C11,
C12 to 0 in the next available DS3 frame when operating in the C-bit parity
mode. To send an additional error, the microprocessor must first set this bit
to 0 before again setting it to 1.
1 will generate and transmit a P-bit error by inverting both P-bits in the next
available DS3 frame. To send an additional error, the microprocessor must
first set this bit to 0 before again setting it to 1.
1 will generate and transmit a C-bit parity error (C7, C8 and C9 inverted) in
the next available DS3 frame when operating in the C-bit parity mode. To
send an additional error, the microprocessor must first set this bit to 0
before again setting it to 1.
Test Counter: This bit should be set to 0.
Excessive Zeros Enable: When set to 1, the EXZ events are counted in
the CVEXZ counter.
Coding Violation Counter Enable: Setting this bit to 1 disables the
FORCECP , FORCEPP and FORCEFEBE input pins from performing their
original force error functions and allows these functions to be performed
instead by setting to 1 bits 3, 4 and 5 of this register. The FORCECP input
pin is then defined as the CVCNT (coding violation) input pin and the
FORCEPP input pin as the EXZCNT (excessive zeros) input pin to the
CVEXZ 16-bit counter in the registers at Addresses 12H and 13H.
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DATA SHEET
Description
TXC-03401B
TXC-03401B-MB
Ed. 6, June 2001
DS3F