LAN9211-ABZJ Standard Microsystems (SMSC), LAN9211-ABZJ Datasheet - Page 13
LAN9211-ABZJ
Manufacturer Part Number
LAN9211-ABZJ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9211-ABZJ.pdf
(147 pages)
Specifications of LAN9211-ABZJ
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
1.11
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9211 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9211 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits
wide. The LAN9211 can be interfaced to either Big-Endian or Little-Endian processors and includes
mixed endian support for FIFO accesses.
Host Bus Interface (SRAM Interface)
DATASHEET
13
Revision 2.7 (03-15-10)
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