FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 14

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Pin List GD16556 - Receiver (continued on next page)
Data Sheet Rev.: 23
Mnemonic:
DI, DIN
DIREF, DIREFN
BP, BPN
BPEN
LB, LBN
LBCK, LBCKN
LBEN
RSEL1, RSEL2
MSEL1, MSEL2
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DO13
DO14
DO15
CKO, CKON
CKREFA, CKREFAN
DO0N
DO1N
DO2N
DO3N
DO4N
DO5N
DO6N
DO7N
DO8N
DO9N
DO10N
DO11N
DO12N
DO13N
DO14N
DO15N
Pin No.:
16, 14
17, 13
69, 70
71, 72
90, 91
67, 66
65, 64
63, 62
61, 60
59, 58
57, 56
55, 54
53, 52
49, 48
47, 46
45, 44
43, 42
41, 40
39, 38
37, 36
35, 34
74, 75
87, 86
8, 7
4, 5
20
6
ANALOG input
LVDS output
LVDS output
LVTTL input
LVTTL input
LVTTL input
LVTTL input
Termination
CML output
CML output
CML output
LVDS input
Pin Type:
*.
*.
*.
GD16556/GD16557*
Pins DI/DIN may be swapped with pins DIREF/DIREFN respec-
tively.
nation.
Differential. CDR bypass data output. Terminated with 50 W to
VDD on-chip.
Enables CDR bypass data output when logic “0". The pin is sup-
plied with a 16 kW pull-up resistor.
Differential. Loop-back data output. Terminated with 50 W to VDD
on-chip.
Differential. Loop-back clock output. Terminated with 50 W to VDD
on-chip.
Loop-back enable. This pin enables the loop-back clock and data
outputs when logic ”0". The pin is supplied with a 16 kW pull-up
resistor.
Rate select pins. The pins are supplied with a 16 kW pull-up resis-
tor.
1.250 Gbit/s
622 Mbit/s
155 Mbit/s
2.488 Gbit/s (default)
Select for 15/14, 16/15 and 32/31 overhead bit rates. These pins
select the divide ratio tuning the on-chip VCO frequency. The pins
are supplied with a 16 kW pull-up resistor.
Divide by
56
60
62
64 (default)
Refer to Table 1 on
applic.
Differential. Data output. The differential output impedance is
100 W. The LVDS output must be terminated with an 100 W im-
pedance DC-path between the differential output.
Differential. Recovered clock output. The differential output im-
pedance is 100 W. The LVDS output must be terminated with an
100 W impedance DC-path between the differential output.
Differential. CDR reference clock. In transponder systems
CKREFA or CKREFB should be connected to the output signal
RECCK from the GD16557 device. The input impedance is 100 W
differential. (100 W on-chip termination resistor).
Description:
Differential AC or DC coupled data inputs to the Limiting Amplifier.
Termination for DI and DIN. Refer to
MSEL1 MSEL2
0
0
1
1
page 11
RSEL1 RSEL2
0
0
1
1
0
1
0
1
for configuration in transponder
0
1
0
1
Figure 12
and
13
Page 14 of 28
for termi-