FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 8

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

The Transmitter – GD16557
General
The GD16557 is an on-the-fly program-
mable multi-bitrate multiplexer with em-
phasis put on transponder applications.
The device is capable of multiplexing
16 independent low speed channels into
one serial bit stream at 155 Mbit/s,
622 Mbit/s, 1.250 Gbit/s or 2.488 Mbit/s.
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (refer to
The device can be either counter or for-
ward clocked.
Low-speed data and clock I/O are LVDS/
LVPECL compatible. The high-speed
outputs are open collectors (CML-type).
Select pins are LVTTL compatible. The
LVTTL inputs are internally pulled high
by default. The VCXO clock inputs are
LVPECL compatible.
The device operates from a single 3.3 V
positive power-supply and the consump-
tion is 1.3 W (typ.).
Figure 14.GD16557 - Block diagram
Data Sheet Rev.: 23
DI0N..15N
VCXOSEL
XCK1N
XCK2N
DI0..15
VCKN
XCK1
XCK2
VSEL
CKIN
VCK
CKI
Figure
19).
16
R
V
R
V
Detect.
Detect.
Detect
Phase
Phase
Freq.
Lock
Freq.
MUX
16:1
DOWN
DOWN
UP
UP
Digital “Wrapping” Modes
The fraction is chosen by the signals
MSEL1 and MSEL2.
outlines the constraints on the bit rates
with respect to the VCXO frequencies.
Select signal settings are listed along.
The table is valid for the transponder sys-
tem shown on
Clock Generator Circuit
The Clock Generator circuit in the
GD16557 is much alike the one in the re-
ceiver GD16556. Please refer to the dis-
cussion in the section Clock Generator
Circuit in the GD16556 description.
Counter Clocking Scheme
When the GD16557 is used in tran-
sponder applications the input reference
clock to the transmitter (CKI, CKIN) is
generated by the receiver GD16556.
Please refer to
CHAP
CHAP
GD16556/GD16557*
4
Figure
Figure 10.
Table 1
1.
/8, /16
VCO
/2, /4
2
on
page 11
/4, /16
/1, /2
2
4
In non-transponder applications the
GD16557 may be operated with jitter
clean-up (including VCXO) or without
leaving the possibility to omit the VCXO.
If operation is desired without the VCXO
(i.e. omitting the double PLL jitter-clean
up) the reference clock input VCK is
available. Select between the clock in-
puts XCK1/XCK2 and VCK through the
signal VSEL.
The reference clock frequency should in
any case be chosen according to Table 1
on
To ease the interfacing between the
GD16557 and the system ASIC the rela-
tion between the counter clock (CNTCK)
and the input data (DI0..15) is adjustable.
Pins PHA1 and PHA2 define the valid
timing relation.
Note:
/56, /60
/62, /64
page 11.
Flop
Flip
/16
D-
When enabling LBEN or
BPEN the VCO is disabled for
noise reduction.
Phase
Adj.
Page 8 of 28
DO
DON
CKO
CKON
CNTCK
CNTCKN
PHA1
PHA2
RECCK
RECCKN
VDD
VDDA
VEE
VEEA
VCMLT1..3