FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 17

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Pin List GD16557 - Transmitter (continued on next page)
Data Sheet Rev.: 23
Mnemonic:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12
DI13
DI14
DI15
CKI, CKIN
XCK1, XCK1N
XCK2, XCK2N
VCXOSEL
BP, BPN
BPEN
PHA1, PHA2
RSEL1, RSEL2
LB, LBN
LBEN
LBCK, LBCKN
VCK, VCKN
VSEL
DI0N
DI1N
DI2N
DI3N
DI4N
DI5N
DI6N
DI7N
DI8N
DI9N
DI10N
DI11N
DI12N
DI13N
DI14N
DI15N
Pin no.:
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
48, 49
52, 53
54, 55
56, 57
58, 59
60, 61
62, 63
64, 65
66, 67
75, 74
78, 77
83, 82
17, 19
27, 29
21, 23
87, 86
4, 5
6, 7
85
25
84
2
LVPECL input.
LVPECL input.
LVTTL input.
LVTTL input.
LVTTL input.
LVTTL input.
LVTTL input.
LVTTL input.
LVDS input.
LVDS input
CML input.
CML input.
CML input
Pin type:
*.
*.
GD16556/GD16557*
Description:
Differential data inputs. The input impedance is 100 W differential.
(Terminated on-chip with 100 W resistor).
Differential reference clock input. In transponder systems this in-
put should be connected to the output FCK from the receiver de-
vice GD16556. The input impedance is 100 W differential.
(Terminated on-chip with 100 W resistor).
Differential clock input. To be used for VCXO clock.
VCXO select. ”1" (default) selects XCK1, XCK1N and “0" selects
XCK2, XCK2N. The pin is supplied with a 16 kW pull-up resistor.
Differential. When in bypass mode data is input through these
pins. Terminated with 50 W to VCMLT1.
Bypass enable. When logic ”0" then data is input from BN, BP.
The pin is supplied with a 16 kW pull-up resistor. When this signal
is logic “0” the VCO is disabled.
Phase adjust. Adjusts the phase between the counter clock
CNTCK and the input data. The pin is supplied with a 16 kW
pull-up resistor.
0°
180°
90°
270° (default)
Rate select pins. The pins are supplied with a 16 kW pull-up resis-
tor.
1.250 Gbit/s
622 Mbit/s
155 Mbit/s
2.488 Gbit/s (default)
Differential. Data signal input for loop-back operation. Terminated
with 50 W to VCMLT2.
Loop-back select. When logic “0" then outputs DO, DON and
CKO, CKON are fed from LB, LBN and LBCK, LBCKN. When this
signal is logic “0” the VCO is disabled.
Differential. Clock signal input for loop-back operation. Termi-
nated with 50 W to VCMLT3.
Differential. External clock input for Phase Frequency Detector.
To be used when operating without jitter-clean up (i.e. without
double PLL).
Input select for Phase Frequency Detector. The pin is supplied
with a 16 kW pull-up resistor.
“0" selects VCKI, VCKIN
“1" (default) selects XCK1/XCK2
PHA1
0
0
1
1
PHA2
0
1
0
1
RSEL1 RSEL2
0
0
1
1
0
1
0
1
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