FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 3

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

sures that the transponder system meets
the jitter specifications.
The core circuit is illustrated on
For simplicity the system ASIC and con-
nections to this device have been omit-
ted. Also, the PLLs have been somewhat
simplified omitting the charge pumps and
loop-filters.
Referring to
the system is as follows; looking at the
CDR device GD16556 the incoming high-
speed data signal is sampled by the
bang-bang detector. The bang-bang de-
tector outputs a signal that drives a
charge pump and hence controls the
on-chip VCO in the CDR. This causes
the VCO frequency to match the data fre-
quency. A reference frequency for the
CDR is supplied from the VCXO located
on the transmit side. The reference fre-
quency assures that the VCO frequency
does not deviate too much from the (ex-
pected) bit rate. Since the CDR in the re-
ceiver needs to be within 500 ppm of the
bit rate, the VCXO frequency should not
deviate more than 200 ppm (TBD) from
its proper centre frequency under any
conditions. Please refer to the section on
the GD16556 device on
tailed discussion of the CDR functional-
ity. Valid VCXO centre frequencies are
outlined on Table 1 on
Turning to the transmit device GD16557
the device implements a double PLL to-
pology. The double PLL is required to
make the system exceed the ITU-T /
Bellcore jitter recommendations inde-
pendent of the bit rate. On the CDR side
a trade-off exists between jitter-tolerance
and jitter-transfer. It is difficult to achieve
a proper jitter-tolerance and simulta-
neously a proper jitter-transfer no matter
the bit rate not having the possibility to
modify the loop-filter. However, by imple-
menting a PLL with a low bandwidth (typ.
less than 10 kHz) it is possible to equal-
ize penalty in jitter- transfer. The result is
an excellent jitter- tolerance no matter
the bit rate. The drawback of this solution
is the need for a high-Q oscillator. Since
it is not possible to realise a high-Q
on-chip oscillator the high-Q oscillator is
added as an external crystal type VCO
(VCXO).
implemented in the GD16557. The
VCXO is locked to the divided clock out-
put from the CDR device. Now, the trans-
mitter on-chip VCO is locked to the
VCXO in a second PLL. This causes the
VCO to track the VCXO achieving supe-
rior phase-noise properties of the
high-speed output data.
The transponder system allows for in-
creased bit rates. The use of increased
standard bit rates is commonly known as
“digital wrapping”. The chip set supports
digital wrapping by implementing pro-
grammable frequency dividers
Data Sheet Rev.: 23
Figure 2
Figure 2
shows the double PLL
the functionality of
page 11.
page 5
Figure 2
for a de-
f
(prescalers). By proper setting of the
dividers the transponder system will com-
ply with bit rates equal to a standard bit
rate ( STM-1 / OC3, STM-4 / OC12,
STM-16 / OC48, GE) multiplied by a frac-
tion larger than one. Supported fractions
are 15/14, 16/15 and 32/31.
Supporting digital wrapping corresponds
with an ability to tune the VCOs in the
CDR and transmit device onto the proper
frequency. Basic frequency synthesis is
applied to implement this functionality.
The principle is illustrated on
choosing the frequency of the reference
clock signal as a standard bit rate fre-
quency (denoted f
the frequency of the VCO (denoted f
becomes:
The on-chip frequency dividers imple-
ments divide by 56, 60, 62 and 64. Sig-
nals MSEL1 and MSEL2 choose the
divide ratio. It is the responsibility of the
system to configure the GD16556/
GD16557 with respect to the bit rate
(RSEL1, RSEL2) and the overhead frac-
tion factor (MSEL1, MSEL2). Table 1 on
page 11
frequencies with respect to the settings
of RSEL1, RSEL2 and MSEL1, MSEL2.
VCO
=
f
STANDARD
outline the recommended VCXO
GD16556/GD16557*
M
´
N
STANDARD
) divided by M,
Figure
3. By
VCO
)
Page 3 of 28